Abstract: A barrier layer stack. The barrier layer stack includes a semiconductor process wafer comprising an exposed conductive region, a first barrier layer stack comprising at least one TiN and one Ti layers overlying and contacting the conductive region, wherein the TiN layer is contacted with the Ti layer, and an overlying aluminum alloy layer in contact with the first barrier layer stack.

Abstract: A barrier layer stack. The barrier layer stack includes a semiconductor process wafer comprising an exposed conductive region, a first barrier layer stack comprising at least one TiN and one Ti layers overlying and contacting the conductive region, wherein the TiN layer is contacted with the Ti layer, and an overlying aluminum alloy layer in contact with the first barrier layer stack.

Abstract: An improved barrier layer stack and method for forming the same for preserving an aluminum alloy interconnect resistivity, the method comprising providing a semiconductor process wafer comprising an exposed conductive region; forming a first barrier layer comprising a barrier layer stack over the exposed conductive region comprising one of a TiN or Ti layer in contact with the conductive region; forming at least one additional barrier layer comprising the barrier layer stack to form an alternating sequence of TiN and Ti layers; forming an uppermost barrier layer of TiN comprising the barrier layer stack; forming an overlying aluminum alloy region in contact with the uppermost barrier layer; and, subjecting the semiconductor process wafer to at least one process comprising a temperature of greater than temperatures greater than about 350° C.

Abstract: An improved barrier layer stack and method for forming the same for preserving an aluminum alloy interconnect resistivity, the method comprising providing a semiconductor process wafer comprising an exposed conductive region; forming a first barrier layer comprising a barrier layer stack over the exposed conductive region comprising one of a TiN or Ti layer in contact with the conductive region; forming at least one additional barrier layer comprising the barrier layer stack to form an alternating sequence of TiN and Ti layers; forming an uppermost barrier layer of TiN comprising the barrier layer stack; forming an overlying aluminum alloy region in contact with the uppermost barrier layer; and, subjecting the semiconductor process wafer to at least one process comprising a temperature of greater than temperatures greater than about 350 ° C.

Abstract: The invention offers a solution to several problems associated wit IC packages that use a top layer of molded plastic. This has been achieved by inter-posing a dummy layer of dielectric material between the upper surface of the integrated circuit wafer and the molded plastic layer. This dummy layer is patterned and etched so that its surface becomes an alternating series of valleys and ridges, care being taken to ensure that all wiring lines are protected by being within ridges. This structure serves both to protect the wiring lines during the application of the molded plastic and, because of the large surface area of contact between plastic and wafer, excellent adhesion of the molded plastic to the wafer is obtained.