Abstract: A method includes forming a gate stack, and etching the gate stack to form a trench penetrating through the gate stack. A dielectric isolation region underlying the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench. The method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first portion and the second portion of the gate stack, and performing a second deposition process to form a second dielectric layer on the first dielectric layer. The second dielectric layer fills the trench. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

Abstract: Provided are semiconductor devices and methods for manufacturing semiconductor devices. A method deposits conformal material to form a conformal liner in the trench and modifies the conformal liner such an upper liner portion is modified more than a lower liner portion. The deposition and modifying steps are repeated while a rate of deposition of the conformal material over a non-modified surface of the conformal liner is faster than a rate of deposition of the conformal material over a modified surface of the conformal liner to form a remaining unfilled gap with a V-shape. The method further includes depositing a conformal material in the remaining unfilled gap.

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.

Abstract: Transistor gate isolation structures and methods of forming the same are provided. In an embodiment, a device includes: an isolation region; a first gate structure on the isolation region; a second gate structure on the isolation region; and a gate isolation structure between the first gate structure and the second gate structure in a first cross-section, an upper portion of the gate isolation structure having a first concentration of an element, a lower portion of the gate isolation structure having a second concentration of the element, the first concentration different from the second concentration, the lower portion extending continuously along a sidewall of the first gate structure, beneath the upper portion, and along a sidewall of the second gate structure.

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

Abstract: A display panel includes a plurality of scan lines, a plurality of data lines, a plurality of power lines, a plurality of light emitting units, a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of light emitting units are arranged in an array and adapted to display different colors. In the organic light emitting units with the same color, some parts are connected to the first pixel circuits, and other parts are connected to the second pixel circuits. A first terminal and a second terminal of a first control transistor in the first pixel circuit are sequentially arranged on a forward direction of a first direction, and a first terminal and a second terminal of a second control transistor in the second pixel circuit are sequentially arranged on a reverse direction of the first direction.

Abstract: A display panel includes a plurality of scan lines, a plurality of data lines, a plurality of power lines, a plurality of light emitting units, a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of light emitting units are arranged in an array and adapted to display different colors. In the organic light emitting units with the same color, some parts are connected to the first pixel circuits, and other parts are connected to the second pixel circuits. A first terminal and a second terminal of a first control transistor in the first pixel circuit are sequentially arranged on a forward direction of a first direction, and a first terminal and a second terminal of a second control transistor in the second pixel circuit are sequentially arranged on a reverse direction of the first direction.