Abstract: An image capturing device capable of automatically switching the clock of the memory and a control method thereof. The image capturing device comprises an image capturing module, a display module, an image buffer module, an operating module and a processing module. The operating module increases the clock of the image buffer module to a first clock, and works with the image capturing module to perform an image capturing process. After the image capturing process is finished, the processing module stops a timing generating unit in the operating module from sending a synchronizing signal to the display module, and controls the operating module to decrease the clock of the image buffer module from the first clock to a second clock. Finally, the processing module controls the timing generating unit to re-send the synchronizing signal to the display module.

Abstract: An image capturing device capable of automatically switching the clock of the memory and a control method thereof. The image capturing device comprises an image capturing module, a display module, an image buffer module, an operating module and a processing module. The operating module increases the clock of the image buffer module to a first clock, and works with the image capturing module to perform an image capturing process. After the image capturing process is finished, the processing module stops a timing generating unit in the operating module from sending a synchronizing signal to the display module, and controls the operating module to decrease the clock of the image buffer module from the first clock to a second clock. Finally, the processing module controls the timing generating unit to re-send the synchronizing signal to the display module.

Abstract: A digital camera having a central processing unit with an embedded micro-code engine comprises a system memory capable of storing an instruction, at least one CPU execution unit electrically coupled with the system memory, and at least one micro-code engine electrically coupled with the CPU execution unit. The at least one CPU execution unit receive and decodes the instruction stored in the system memory. In response to the decoded instruction, the CPU execution unit sends commands and instruction parameters to at least one of an arithmetic logic unit of the CPU execution unit and the micro-code engine to execute the instruction. Typically the at least one CPU execution unit and the at least one micro-code engine operate in synchronization to execute the instruction.

Abstract: An image processing system and method thereof for a digital camera are disclosed. The image processing system comprises a sweep control unit, a line extend control unit and a WOI control unit. When the output time of a digital image needs to be prolonged, the line extend control unit will be triggered in order to extend the processing time of the digital image.

Abstract: A digital camera having a central processing unit with an embedded micro-code engine comprises a system memory capable of storing an instruction, at least one CPU execution unit electrically coupled with the system memory, and at least one micro-code engine electrically coupled with the CPU execution unit. The at least one CPU execution unit receive and decodes the instruction stored in the system memory. In response to the decoded instruction, the CPU execution unit sends commands and instruction parameters to at least one of an arithmetic logic unit of the CPU execution unit and the micro-code engine to execute the instruction. Typically the at least one CPU execution unit and the at least one micro-code engine operate in synchronization to execute the instruction.

Abstract: A micro-code engine with a linear shift register comprises at least one shift register and an execution unit. The shift registers contain a plurality of data cells, each of which store at least one data value. The shift register is operable to shift the data values from a first data cell to a second data cell as new data is input into the shift register. The execution unit is electrically coupled to the linear shift register such that when the execution unit performs an algorithm, the execution unit uses the data value stored in the second data cell as an operand. After the execution unit substantially completes the algorithm, the linear shift register shifts a new data value into the second data cell. In response to the linear shift register shifting new data into the second data cell, the execution unit re-performs the algorithm.

Abstract: A method of improving the compression ratio of image data in the form of foreground data printed over background data by arranging both kinds of data pixels into 8 by 8 pixel blocks. All blocks that do not contain at least one pixel to be printed are deleted before compression. The deleted blocks will be entirely background pixels that will be overlaid by foreground pixels, or entirely foreground pixels that will not be printed because they are located outside of foreground masks.

Abstract: A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the "history", stored in a series of shift registers. Each register and associated comparator constitutes a cell. If one or more matches are found the history data is shifted one pixel, the non-matching cells are disabled, and the next input pixel is compared against the contents of the same cells that had the previous matches. The matching is terminated when the longest series of matching pixels is found. The output code is then the length of the matching series of pixels, and the displacement of the first input pixel from the first matching pixel. An encoder generates an initialize signal that resets all of the disabled cells on the same clock cycle on which the output code word is generated. To make the circuit more compact, the cells can be arranged into a square format with one output line for each row and column from the cells to the encoder.

Abstract: A system for changing the source and destination devices of data transfers under software control. Default data transfers are made from numbered source devices to the same-numbered destination devices, the data requests being routed through multiplexers which pair, for example, source 1 with destination 1, source 2 with destination 2, etc. The multiplexer control signals originate in a register which is originally loaded with default control bits. However, in real time, the bits within the control register can be re-loaded to provide outputs other than the default values. Then, the data from a source can be directed to any one of the destination devices.

Abstract: A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.

Abstract: A method is described for determining readiness of devices in a digital data bus system to transfer data signals. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lines for communicating data signals, and control lines for communicating control signals. The bus system also includes a plurality of devices. Each device is connected to the bus and has an address on the bus. At least one device is a source device capable of sending data signals and at least one device is a destination device capable of receiving data signals. A bus controller connects to the bus and controls the bus. The control lines include bus request lines that connect each device to the bus controller for communicating a bus request signal from a device to the bus controller. The bus request signal indicates that the device is ready to send or receive data signals.

Abstract: A new and improved decoder for decoding CCITT compressed image data. This decoder separates all the incoming codes into short codes and long codes. The short codes are sent to the short channel decoder and the long codes are sent to the long channel decoder. At each decoding cycle either the long channel decoder or the short channel decoder is active. The short channel decoder has a twin set decoder which decodes two short codes in parallel and guarantees two bits of decompressed data per decoding cycle. If the decoding of a first code generates a decompressed data of only one bit, then the decompressed data of a second code will be combined with the first decompressed data and the combination will be sent out. This process guarantees at least two bits of decompressed data per decoding cycle. The long channel decoder decodes the long intermediate codes which always generate at least four bits of decompressed data.

Abstract: The present invention is concerned with a self-adjusting document sensor compensating for degradation of the sensor system. A suitable light source and a detector are provided, the output of the detector being fed into an amplifier whose gain depends upon a feedback signal. Periodically, the output of the amplifier is compared to a reference. If the output of the amplifier falls below the reference, a pulse is sent to a ripple counter whose digital output is fed back to the amplifier to change the gain of the amplifier. If the detector is an unbiased photodiode operating in the transconductance mode, the leakage currents and their subsequent effect on output with amplifier gain changes will be minimized.

Abstract: An integrated circuit chip with digital and analog circuits thereon for providing a low cost infrared reflectance densitometer for detecting relative toner density on a photoreceptive surface including several stages of calibration including photodiode detection means 208 for monitoring and controlling the light output from a light emitting diode 206, photodiode means 302 for detecting undesired scattered and reflected background light signals, further photodiode means 304 for detecting the light reflected from said photoreceptive surface as may be affected by toner deposited thereon, an automatic gain control circuit 400 for automatically adjusting the output gain of the reflectance densitometer, and sample and hold circuit means 600 for adjusting the circuit for different effects of the aging, leakage current effects, or other undesired performance characteristics of the circuit components.