Abstract: Disclosed are a low-temperature processing method for improving a 4H—SiC/SiO2 interface based on a supercritical oxynitride, and use thereof. The method includes: performing standard cleaning on a silicon carbide sample to be processed; performing dry-oxygen oxidation on the cleaned silicon carbide sample to grow an oxide layer; placing the silicon carbide sample having the oxide layer on a support in a steady-state supercritical chamber; controlling a pressure and injecting nitrogen-oxygen gas into the supercritical device; increasing a temperature in the supercritical device from 23° C. to 500° C.; maintaining the above supercritical state until the processing ends; reducing a temperature of a reactor to room temperature after reaction ends, reducing the pressure to an atmospheric pressure, and taking out the reactor. The present disclosure allows for effective and quick decrease in the 4H—SiC/SiO2 interface state density, and also a significant decrease in the processing temperature.

Abstract: A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage VON and the turn-off voltage VD to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor.

Abstract: A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage VON and the turn-off voltage VD to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor.