Abstract: A staining kit is provided, including a first pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, CD8, CD45, and CTLA4; a second pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, dendritic cell, and CD45; a third pattern including antibodies against T cell, B cell, NK cell, monocyte, CD8, CD45, CD45RA, CD62L, CD197, CX3CR1 and TCR??; and a fourth pattern including antibodies against B cell, CD23, CD38, CD40, CD45 and IgM, wherein the antibodies of each pattern are labeled with fluorescent dyes. A method of identifying characterized immune cell subsets of a disease and a method of predicting the likelihood of NPC in a subject in the need thereof using the staining kit are also provided.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.

Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A miniaturized voltage-transforming device includes a first circuit board and a second circuit board parallel to and separated from each other by a predetermined distance so that there is no physical connection therebetween, and a transformer having a plurality of primary-side pins and a plurality of secondary-side pins, wherein the transformer is located beside the first circuit board and the second circuit board, and has its primary-side pins and secondary-side pins directly or indirectly connected to the first circuit board and the second circuit board physically, so that the transformer is electrically connected to the first circuit board and the second circuit board via the primary-side pins and the secondary-side pins.

Abstract: An ultralow no-load conduction loss DC converter includes a DC power source, a transformer having a first winding, a first MOSET and a PWM controller at the primary side and a second winding, a third winding, a drive control unit, a rectifier unit and a second MOSFET at the secondary side. The second MOSFET, the drive control unit and the rectifier unit constitutes a combination circuit electrically coupled between one end of the second winding and one end of the third winding. The second MOSFET has set therein a body diode. The second winding and the second MOSFET forms a combination circuit electrically connected to a load. Thus, the decision to turn off the drive control unit is made at the secondary side so that non-load conduction loss can be minimized.

Abstract: A power converter includes a DC power source, a transformer having a first winding, a first MOSFET and a PWM controller at the primary side and a second winding, a drive control unit, a current detection control unit, a comparator and a second MOSFET at the secondary side. The comparator has its input end electrically connected to the current detection control unit and its output end electrically connected to the drive control unit, which is electrically connected to the second MOSFET for synchronous rectification. The second MOSFET is electrically connected to one end of the second winding, having a body diode built therein. The second winding and the second MOSFET constitute a combination circuit electrically connected to a load that has a capacitor electrically connected thereto in a parallel manner. By means of the aforesaid arrangement, conduction loss at a low load is minimized, thereby improving the efficiency at a low load.

Abstract: A miniaturized voltage-transforming device includes a first circuit board and a second circuit board parallel to and separated from each other by a predetermined distance so that there is no physical connection therebetween, and a transformer having a plurality of primary-side pins and a plurality of secondary-side pins, wherein the transformer is located beside the first circuit board and the second circuit board, and has its primary-side pins and secondary-side pins directly or indirectly connected to the first circuit board and the second circuit board physically, so that the transformer is electrically connected to the first circuit board and the second circuit board via the primary-side pins and the secondary-side pins.

Abstract: A power converter includes a DC power source, a transformer having a first winding, a first MOSET and a PWM controller at the primary side and a second winding, a drive control unit, a current detection control unit, a comparator and a second MOSFET at the secondary side. The comparator has its input end electrically connected to the current detection control unit and its output end electrically connected to the drive control unit, which is electrically connected to the second MOSFET for synchronous rectification. The second MOSFET is electrically connected to one end of the second winding, having a body diode built therein. The second winding and the second MOSFET constitute a combination circuit electrically connected to a load that has a capacitor electrically connected thereto in a parallel manner. By means of the aforesaid arrangement, conduction loss at a low load is minimized, thereby improving the efficiency at a low load.

Abstract: A power converter includes at least one electric control switch, an electric current detecting and converting unit, a power controller, and a voltage detecting and controlling unit at the primary side; and a synchronous rectifying circuit, two MOSFETs, and an oscillating loop. During the actual operation, electric current detecting and converting unit outputs an AC voltage signal to the power controller and outputs a DC voltage signal to the voltage detecting and controlling unit, and then voltage detecting and controlling unit compares with a reference voltage to turn off the synchronous rectifying circuit at the no-load mode and to rectify via a body diodes of the MOSFETs. Accordingly, the power converter can reduce the power wastage at the no-load mode to be energy-saving.

Abstract: A power converter includes at least one electric control switch, an electric current detecting and converting unit, a power controller, and a voltage detecting and controlling unit at the primary side; and a synchronous rectifying circuit, two MOSFETs, and an oscillating loop. During the actual operation, electric current detecting and converting unit outputs an AC voltage signal to the power controller and outputs a DC voltage signal to the voltage detecting and controlling unit, and then voltage detecting and controlling unit compares with a reference voltage to turn off the synchronous rectifying circuit at the no-load mode and to rectify via a body diodes of the MOSFETs. Accordingly, the power converter can reduce the power wastage at the no-load mode to be energy-saving.

Abstract: A synchronous rectifier drive circuit includes a primary side and a secondary side. The primary side has a first coil winding, a first MOSFET, an auxiliary MOSFET, an auxiliary capacitor, and an input power source. The secondary side has a second coil winding, a DC voltage source, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and an inductor. The gate of the second MOSFET is connected with the source of the fourth MOSFET. The gate of the third MOSFET is connected with the source of the fifth MOSFET. The inductor has two ends, one of which is connected with the drain of the third MOSFET. Accordingly, the synchronous rectifier drive circuit can lessen the variation of pulse wave of the drive voltage and refrain the surge voltage to protect the electronic elements.