Abstract: In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.

Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.

Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.

Abstract: In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.

Abstract: A method and system are provided for acquiring and combining images captured by a microscope. The method comprises: capturing a new image from the microscope using an imaging device; comparing the new image against a previous image to provide an estimated position of the new image; identifying neighboring key frames of a scan stored in memory based on the estimated position of the new image; comparing the new image to the identified key frames to determine a relative displacement of the new image from the neighboring key frames; and determining a position of the new image based on the relative displacement of the new image. The system includes: a microscope; a camera coupled to the microscope for capturing images through the microscope; and a computing device coupled to the camera, the computing device comprising: a memory; and a processor configured and adapted to perform a method as described herein.

Abstract: A microscopy imaging system and method for rendering a mosaic representation of an object from a series of image frames of the object are disclosed. A current image frame is processed to determine its relative location or position within the mosaic representation based on relative displacement of the current image from one or more keyframes. Once the current image frame's position has been determined, it is rendered along with its neighboring keyframes to provide the mosaic representation of the object.

Abstract: A microscopy imaging system and method for rendering a mosaic representation of an object from a series of image frames of the object are disclosed. A current image frame is processed to determine its relative location or position within the mosaic representation based on relative displacement of the current image from one or more keyframes. Once the current image frame's position has been determined, it is rendered along with its neighboring keyframes to provide the mosaic representation of the object.