Patents by Inventor Li-Hsien HUANG
Li-Hsien HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11062978Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.Type: GrantFiled: September 30, 2019Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
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Publication number: 20210183813Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Der-Chyang Yeh, Li-Hsien Huang, Ta-Hsuan Lin, Ming-Shih Yeh
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Patent number: 11037899Abstract: A package structure includes a first die, at least one second die, a semiconductor substrate and a glue layer. The semiconductor substrate includes no active devices. The glue layer is disposed between the at least one second die and the semiconductor substrate. The glue layer has a top surface adhered to the least one second die and a bottom surface adhered to a topmost surface of the semiconductor substrate. A total area of the bottom surface of the glue layer is substantially equal to a total area of the topmost surface of the semiconductor substrate, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the glue layer.Type: GrantFiled: May 29, 2020Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
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Patent number: 11018025Abstract: A method includes forming a dielectric layer over a conductive feature, forming an opening in the dielectric layer, and plating a metallic material to form a redistribution line electrically coupled to the conductive feature. The redistribution line includes a via in the opening, and a metal trace. The metal trace includes a first portion directly over the via, and a second portion misaligned with the via. A first top surface of the first portion is substantially coplanar with a second top surface of the second portion of the metal trace.Type: GrantFiled: July 31, 2015Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Li-Hsien Huang
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Patent number: 11004818Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.Type: GrantFiled: June 29, 2020Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
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Publication number: 20210111120Abstract: A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Guan-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming-Shih Yeh
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Publication number: 20210104416Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.Type: ApplicationFiled: November 23, 2020Publication date: April 8, 2021Inventors: Hsien-Wei Chen, Der-Chyang Yeh, Li-Hsien Huang
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Publication number: 20210082855Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
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Patent number: 10950575Abstract: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.Type: GrantFiled: July 24, 2018Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Hua-Wei Tseng
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Publication number: 20210066263Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.Type: ApplicationFiled: February 19, 2020Publication date: March 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Li-Hsien Huang, Tien-Chung Yang, Ming-Shih Yeh
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Publication number: 20210050305Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.Type: ApplicationFiled: November 2, 2020Publication date: February 18, 2021Inventors: Chi-Hsi Wu, Hsien-Wei Chen, Li-Hsien Huang, Tien-Chung Yang
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Publication number: 20210035953Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.Type: ApplicationFiled: October 19, 2020Publication date: February 4, 2021Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
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Publication number: 20210005515Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.Type: ApplicationFiled: September 15, 2020Publication date: January 7, 2021Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
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Patent number: 10879224Abstract: A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.Type: GrantFiled: January 29, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hsien Huang, Ming-Shih Yeh
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Patent number: 10872855Abstract: A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.Type: GrantFiled: January 28, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Guan-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming-Shih Yeh
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Patent number: 10867928Abstract: A semiconductor device and the manufacturing method thereof are provided. The semiconductor device includes a package structure, a first die, a first containment structure, a pre-fill layer, and a plurality of conductive terminals. The package structure includes an attach zone, a keep-out zone around the attach zone. The first die is disposed on the package structure in the attach zone and electrically connected to the package structure. The first containment structure is disposed within the keep-out zone of the package structure and surrounds the first die. The pre-fill layer is disposed between the package structure and the first die and between the first containment structure and the first die, where the pre-fill layer is constrained within the first containment structure. The conductive terminals are disposed on the package structure, distributed around the keep-out zone of the package structure, and electrically connected to the package structure.Type: GrantFiled: March 26, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Chung Lu, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Yueh-Ting Lin, Ming-Shih Yeh
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Publication number: 20200381373Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
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Patent number: 10854565Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.Type: GrantFiled: September 21, 2018Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
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Patent number: 10847383Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.Type: GrantFiled: October 31, 2019Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hsien-Wei Chen, Der-Chyang Yeh, Li-Hsien Huang
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Publication number: 20200365563Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The chip package structure includes a first molding layer surrounding the first chip and the second chip. The first molding layer is a single layer structure. A first boundary surface between the passivation layer and the second molding layer extends toward the first chip. The chip package structure includes a second molding layer surrounding the third chip and the first molding layer. A first bottom surface of the first molding layer and a second bottom surface of the second molding layer are substantially coplanar.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu CHEN, Li-Hsien HUANG, An-Jhih SU, Hsien-Wei CHEN