Patents by Inventor Li-Hsin Tseng
Li-Hsin Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8669658Abstract: A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.Type: GrantFiled: July 24, 2007Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mon-Chin Tsai, Hsiu-Mei Yo, Chien-Min Lin, Chia-Jen Cheng, Li-Hsin Tseng
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Patent number: 8355628Abstract: The invention provides a compact camera module. The compact camera module includes an image sensing device, a set of optical elements, and a zooming device. The set of optical elements connects to the image sensing device, and comprises a lens set. The zooming device connects to the set of optical elements for adjusting a distance between the lens set and the image sensing device. The zooming device directly electrically joins with the image sensing device.Type: GrantFiled: March 6, 2009Date of Patent: January 15, 2013Assignees: VisEra Technologies Company Limited, OmniVision Technologies, Inc.Inventors: Shin-Chang Shiung, Chieh-Yuan Cheng, Li-Hsin Tseng
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Publication number: 20120252526Abstract: A telephone device capable of sensing a radio frequency identification (RFID) tag includes: a control module, a display unit, and a handset unit. The control module has a database and a processor electrically connected to the database. The display unit is electrically connected to the processor of the control module. The handset unit has a housing, a telephone module, a radio frequency identification reader, a switch, and a transmitter, wherein the telephone module, the radio frequency identification reader, the switch and the transmitter are disposed in the housing. The telephone module has a listening component and a speaking component. The radio frequency identification reader has a signal transceiver. The switch is selectivity conducting to the telephone module or the radio frequency identification reader. The transmitter is electrically connecting to the processor of the control module and the switch. Thus, the telephone device has radio frequency identification and communicating functions.Type: ApplicationFiled: April 4, 2011Publication date: October 4, 2012Applicant: FLYTECH TECHNOLOGY CO. LTD.Inventors: TAI-SENG LAM, Chiung-Chi Lin, Li Hsin Tseng
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Publication number: 20120243677Abstract: A telephone device having barcode scanning capability includes: a control module, a display unit, and a handset. The control module has a database and a processor electrically connected to the database. The display unit is electrically connected to the processor of the control module. The handset unit has a housing, a telephone module, a scanner, a switch, and a transmitter module, wherein the telephone module, the scanner, the switch and the transmitter module are disposed in the housing. The housing has a scanning port formed thereof. The telephone module has a listening component and a speaking component. The scanner has an optical reading unit corresponding to the scanning port of the housing. The switch is selectivity conducting to the telephone module or the scanner. The transmitter module is electrically connecting to the processor of the control module and the switch. Thus, the telephone device has scanning and communicating functions.Type: ApplicationFiled: March 25, 2011Publication date: September 27, 2012Applicant: FLYTECH TECHNOLOGY CO., LTD.Inventors: TAI-SENG LAM, Chiung-Chi Lin, Li Hsin Tseng
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Patent number: 7964936Abstract: Electronic device packages with electromagnetic compatibility (EMC) coating thereon are presented. An electronic device package includes a chip scale package having a CMOS image sensor (CIS) array chip and a set of lenses configured with an aperture. An encapsulation is molded overlying the chip scale package. A shield is atop the encapsulation. A frame fixes the set of lenses to the encapsulation. An electromagnetic compatibility (EMC) coating is formed on the encapsulation to prevent electromagnetic interference.Type: GrantFiled: July 10, 2008Date of Patent: June 21, 2011Assignee: VisEra Technologies Company LimitedInventors: Shin-Chang Shiung, Tzu-Han Lin, Chieh-Yuan Cheng, Li-Hsin Tseng
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Publication number: 20100226633Abstract: The invention provides a compact camera module. The compact camera module includes an image sensing device, a set of optical elements, and a zooming device. The set of optical elements connects to the image sensing device, and comprises a lens set. The zooming device connects to the set of optical elements for adjusting a distance between the lens set and the image sensing device. The zooming device directly electrically joins with the image sensing device.Type: ApplicationFiled: March 6, 2009Publication date: September 9, 2010Inventors: Shin-Chang SHIUNG, Chieh-Yuan CHENG, Li-Hsin TSENG
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Publication number: 20100006965Abstract: Electronic device packages with electromagnetic compatibility (EMC) coating thereon are presented. An electronic device package includes a chip scale package having a CMOS image sensor (CIS) array chip and a set of lenses configured with an aperture. An encapsulation is molded overlying the chip scale package. A shield is atop the encapsulation. A frame fixes the set of lenses to the encapsulation. An electromagnetic compatibility (EMC) coating is formed on the encapsulation to prevent electromagnetic interference.Type: ApplicationFiled: July 10, 2008Publication date: January 14, 2010Inventors: Shin-Chang Shiung, Tzu-Han Lin, Chieh-Yuan Cheng, Li-Hsin Tseng
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Publication number: 20090026608Abstract: A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Inventors: Mon-Chin Tsai, Hsiu-Mei Yo, Chien-Min Lin, Chia-Jen Cheng, Li-Hsin Tseng
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Publication number: 20080303154Abstract: An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask.Type: ApplicationFiled: June 11, 2007Publication date: December 11, 2008Inventors: Hon-Lin Huang, Boe Su, Li-Hsin Tseng, Chia-Jen Cheng, Hsiu-Mei Yu
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Patent number: 7459386Abstract: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening.Type: GrantFiled: November 16, 2004Date of Patent: December 2, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsin Tseng, Gil Huang, Huei-Mei Yu, Chia-Jen Cheng, Ken Sun, Chien-Tung Yu, Blenny Chang, Chih Yang Chan, Jian-Wen Luo, Owen Chen
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Publication number: 20080251916Abstract: A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over the aluminum electrically conductive element, and a copper layer disposed over the tantalum layer, where the UBM structure is configured to receive a solder ball thereon.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHIU SUNG CHENG, HSIU-MEI YU, CHIA-JEN CHENG, C.T. CHUANG, CHUN-YEN LO, LI-HSIN TSENG
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Patent number: 7187078Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.Type: GrantFiled: September 13, 2004Date of Patent: March 6, 2007Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Tzu-Han Lin, Huei-Mei Yu, Chia-Jen Cheng, Chun-Yen Lo, Li-Hsin Tseng, Boe Su, Simon Lu
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Patent number: 7122458Abstract: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over the seed layer to expose a portion thereof over the bonding pad, and a metal layer is then formed thereon. A sacrificial layer is then formed over the substrate and the sacrificial layer over the patterned mask layer is removed. The conductive film exposed by the metal layer and the remaining sacrificial layer is then removed, leaving a pad redistribution layer for the bonding pad.Type: GrantFiled: July 22, 2004Date of Patent: October 17, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Jen Cheng, Hui-Mei Yu, Li-Hsin Tseng, Tzu-Han Lin, Ching-Chiang Wu, Chun-Yen Lo, Li-Chuan Huang, Boe Su
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Publication number: 20060105560Abstract: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening.Type: ApplicationFiled: November 16, 2004Publication date: May 18, 2006Inventors: Li-Hsin Tseng, Gil Huang, Huei-Mei Yu, Chia-Jen Cheng, Ken Sun, Chien-Tung Yu, Blenny Chang, Chih Chan, Jian-Wen Luo, Owen Chen
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Publication number: 20060087039Abstract: A novel under-bump metallization (UBM) structure for providing electrical communication is described. The UBM structure includes a plurality of metallic layers, which are deposited onto a bonding pad of a semiconductor device, such as a semiconductor chip. The UBM structure may be provided as an interface between the bonding pad and a solder bump deposited over the UBM structure. In one example, the UBM structure includes layers of nickel and copper in which nickel is the upper layer in contact with the solder bump and copper is the lower layer in contact with the bonding pad. The nickel layer is formed to include a downwardly depending perimeter portion, which serves as a cover to the copper layer of the UBM structure. Accordingly, the copper layer is shielded from contact with the solder material during the reflow process, thereby avoiding undesirable reactions between the copper and solder.Type: ApplicationFiled: October 22, 2004Publication date: April 27, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHIU SUNG CHENG, SHIH-MING CHEN, H.M. YU, KUO-WEI LIN, LI-HSIN TSENG
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Publication number: 20060055035Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.Type: ApplicationFiled: September 13, 2004Publication date: March 16, 2006Inventors: Tzu-Han Lin, Huei-Mei Yu, Chia-Jen Cheng, Chun-Yen Lo, Li-Hsin Tseng, Boe Su, Simon Lu
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Publication number: 20060019480Abstract: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over the seed layer to expose a portion thereof over the bonding pad, and a metal layer is then formed thereon. A sacrificial layer is then formed over the substrate and the sacrificial layer over the patterned mask layer is removed. The conductive film exposed by the metal layer and the remaining sacrificial layer is then removed, leaving a pad redistribution layer for the bonding pad.Type: ApplicationFiled: July 22, 2004Publication date: January 26, 2006Inventors: Chia-Jen Cheng, Hui-Mei Yu, Li-Hsin Tseng, Tzu-Han Lin, Ching-Chiang Wu, Chun-Yen Lo, Li-Chuan Huang, Boe Su
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Patent number: 6696356Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.Type: GrantFiled: December 31, 2001Date of Patent: February 24, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsin Tseng, Hsiu-Mei Yu, Ta-Yang Lin, Fang-Chung Liu, Kai-Ming Ching, Tung-Heng Shie
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Publication number: 20030124832Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.Type: ApplicationFiled: December 31, 2001Publication date: July 3, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsin Tseng, Hsiu-Mei Yu, Ta-Yang Lin, Fang-Chung Liu, Kai-Ming Ching, Tung-Heng Shie
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Patent number: 6486054Abstract: The present invention teaches how greater solder ball height can be achieved without the need to sacrifice areal density. The mold in which the solder is formed, is created in two steps. In a first exposure, a negative photoresist (preferably DFR) is patterned to form a conventional cylindrical mold. However, exposure and development time are adjusted in such a way that a layer of unexposed and undeveloped resist of reduced thickness remains covering the floor of the mold. This residual resist layer is given a second exposure and, after development, forms an annular insert in the bottom of the first mold. After the mold has been filled with solder (either through electroplating or by using solder paste) it is removed, the result being a solder bump made up of two contiguous coaxial cylinders the upper one having the larger diameter. After remelt, bumps having this shape form oblate spheroids rather than spheres.Type: GrantFiled: January 28, 2002Date of Patent: November 26, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yang-Tung Fan, Hsiu-Mei Yu, Li-Hsin Tseng, Kuang-Peng Lin, Ta-Yang Lin