Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.

Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

Abstract: A method includes receiving a first wafer having a first device layer on a first semiconductor substrate, receiving a second wafer having a second device layer on a second semiconductor substrate, forming a first groove along a first scribing channel of the first wafer with a non-mechanical cutting process, and forming a second groove along a second scribing channel of the second wafer with the non-mechanical cutting process. The method further includes after the forming of the first and second grooves, bonding the first and second wafers together, and dicing the bonded first and second wafers through the first and second grooves with a mechanical cutting process.

Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall.

Abstract: The current disclosure describes carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.

Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.

Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.

Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

Abstract: A semiconductor package assembly and an electronic device are provided. The semiconductor package assembly includes a base, a system-on-chip (SOC) package, a memory package and a silicon capacitor die. The base has a first surface and a second surface opposite the first surface. The SOC package is disposed on the first surface of the base and includes a SOC die having pads and a redistribution layer (RDL) structure. The RDL structure is electrically connected to the SOC die by the pads. The memory package is stacked on the SOC package and includes a memory package substrate and a memory die. The memory package substrate has a top surface and a bottom surface. The memory die is electrically connected to the memory package substrate. The silicon capacitor die is disposed on and electrically connected to the second surface of the base.

Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.

Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.

Abstract: A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy pattern disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy pattern and the contact pad.

Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

Abstract: The current disclosure describes carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.