Abstract: A filter for eliminating image errors, as well as associated method and TV signal display circuit, is provided to determine the filter coefficients according to the regularity of image errors in an image signal or a TV signal, thereby removing the image errors. The filter includes a plurality of multipliers and an adder. The multipliers receive a plurality of pixel values from a plurality of scan lines, multiply the pixel values by a plurality of corresponding weight coefficients and output the result; the adder sums up the outputs of the multipliers to generate an output pixel value. The errors have a regularity and the corresponding weight coefficients are associated with the regularity such that the errors of the pixel values may be canceled when the adder generates the output pixel value.

Abstract: A de-interlacing method and controller is provided. The de-interlacing method includes steps of de-interlacing based on an ith odd input pixel row of an odd field and an ith even input pixel row of an even field to generate an ith odd output pixel row, where i is a natural number; de-interlacing based on the ith even input pixel row and an (i+1)th odd input pixel row of the odd field to generate an ith even output pixel row; and adjusting i and repeating the above steps to generate a complete interpolated frame.

Abstract: An image processing circuit generating a frame according to a plurality of fields including at least first, second and third fields, comprises a memory unit and a de-interlacing unit. The memory unit stores the first and second fields. The de-interlacing unit receives the third field, and reads the first and second fields from the memory to generate a de-interlaced frame accordingly.

Abstract: A filter for eliminating image errors, as well as associated method and TV signal display circuit, is provided to determine the filter coefficients according to the regularity of image errors in an image signal or a TV signal, thereby removing the image errors. The filter includes a plurality of multipliers and an adder. The multipliers receive a plurality of pixel values from a plurality of scan lines, multiply the pixel values by a plurality of corresponding weight coefficients and output the result; the adder sums up the outputs of the multipliers to generate an output pixel value. The errors have a regularity and the corresponding weight coefficients are associated with the regularity such that the errors of the pixel values may be canceled when the adder generates the output pixel value.

Abstract: A de-interlacing method and controller is provided. The de-interlacing method includes steps of de-interlacing based on an ith odd input pixel row of an odd field and an ith even input pixel row of an even field to generate an ith odd output pixel row, where i is a natural number; de-interlacing based on the ith even input pixel row and an (i+1)th odd input pixel row of the odd field to generate an ith even output pixel row; and adjusting i and repeating the above steps to generate a complete interpolated frame.

Abstract: An image scaler includes a horizontal downscaler, a horizontal upscaler, and a vertical scaling unit. The horizontal downscaler is configured in front of the vertical scaling unit and the horizontal upscaler is configured in back of the vertical scaling unit, so as to operate in coordination with a selective control method. The selective control method controls an image input route depending on horizontal downscaling or upscaling requirements, so as to choose to go through or to bypass the horizontal downscaler or the horizontal upscaler to horizontally and vertically resize an image. In this way, the input signal is processed in only two stages, so that the present invention can not only reduce the process loading of the huge amount of the data volume in the final stage, and also can reduce power consumption.

Abstract: An image processing circuit generating a frame according to a plurality of fields including at least first, second and third fields, comprises a memory unit and a de-interlacing unit. The memory unit stores the first and second fields. The de-interlacing unit receives the third field, and reads the first and second fields from the memory to generate a de-interlaced frame accordingly.

Abstract: An image scaler includes a horizontal downscaler, a horizontal upscaler, and a vertical scaling unit. The horizontal downscaler is configured in front of the vertical scaling unit and the horizontal upscaler is configured in back of the vertical scaling unit, so as to operate in coordination with a selective control method. The selective control method controls an image input route depending on horizontal downscaling or upscaling requirements, so as to choose to go through or to bypass the horizontal downscaler or the horizontal upscaler to horizontally and vertically resize an image. In this way, the input signal is processed in only two stages, so that the present invention can not only reduce the process loading of the huge amount of the data volume in the final stage, and also can reduce power consumption.

Abstract: A method and system are disclosed for counting error rates occurring within an optical compact disk system as data is read from an optically encoded compact disk. In a preferred embodiment error flag data are generated as errors occur within the optical compact disk system. From the error flag data, error flag bits corresponding to errors in reading information from an optically encoded disk are identified for further processing. Further processing includes, among other things, generating an error rate over a predetermined time period. The operation of some or all of the functions within the optical compact disk system may be interrupted upon the exceeding of a predetermined threshold error rate. From the error rate information, the hardware, software and firmware within the optical compact disk system may be optimized for increased performance.

Abstract: A method and system are disclosed for counting errors occurring within an optical compact disk system as data is read from an optically encoded compact disk. In a preferred embodiment error flag data are generated as errors occur within the optical compact disk system. From the error flag data, error flag bits corresponding to errors in reading information from an optically encoded disk are identified for further processing. Further processing includes, among other things, keeping a total count of errors, keeping a count of single occurring errors, keeping a count of multiple occurring errors. Furthermore, by keeping error count information, the operation of the optical compact disk system may be interrupted upon the exceeding of a predetermined threshold. From the error count information the hardware, software and firmware within the optical compact disk system is optimized for increased performance.

Abstract: A method for set-up of a group of parameter values needed in a CD-R or CD-RW write cycle, where the time allotted for set-up is as low as six clock cycles. In a clock cycle from a preceding write cycle, first and second parameter values are read into first and second registers, and a third parameter value is read into a first SRAM. In clock cycles 1-5 of the present write cycle, fourth, fifth, sixth, seventh and eighth parameter values are read into second, third, fourth, fifth and sixth SRAMs. In clock cycle no. 6 or later of the present write cycle, three sums (or differences) of selected combinations of these eight parameter values are calculated and stored, new first and second parameter values are read into first and second registers, and a new third parameter value is read into another SRAM. The method is generalized to K parameters stored in registers, N parameters stored in SRAMs and calculation of M selected linear combinations of the K+N parameter values.

Abstract: Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while the other memory bank is being updated from the other interface terminal. The multiplexer circuitry is controlled by a control register which responds to an operation code whereby either memory bank can be updated while the other memory bank is being read for hardware parameters, for example.