Patents by Inventor Li-Hui Cheng

Li-Hui Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250246503
    Abstract: A package structure is provided. The package structure includes a substrate, a package component bonded to the substrate, a lid disposed over the package component and the substrate, and an interface structure sandwiched between the package component. The package component includes a first die, a second die laterally spaced apart from the first die by an underfill, and a molding compound adjacent the first die and the second die. The interface structure includes an adhesive layer disposed over the underfill and the molding compound, and a thermal interface material (TIM) layer over the adhesive layer, the first die and the second die.
    Type: Application
    Filed: April 25, 2024
    Publication date: July 31, 2025
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng
  • Publication number: 20250210450
    Abstract: A package structure is provided. The package structure includes a substrate, a die bonded to the substrate, a lid disposed over the die and the substrate, and an interface structure sandwiched between the die and the lid and including a first thermal interface material disposed at corners of a top surface of the die, and a second thermal interface material disposed a rest of the top surface of the die. A Young's modulus of the first thermal interface material is smaller than a Young's modulus of the second thermal interface material.
    Type: Application
    Filed: March 13, 2024
    Publication date: June 26, 2025
    Inventors: Chun-Yen Lan, Yu-Hsun Wang, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Yu-Wei Lin
  • Publication number: 20250210541
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes a first ring structure over the wiring substrate and surrounding the chip structure, wherein a first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure.
    Type: Application
    Filed: May 23, 2024
    Publication date: June 26, 2025
    Inventors: Chun-Yen Lan, Yu-Hsun Wang, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20250210455
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Application
    Filed: March 10, 2025
    Publication date: June 26, 2025
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20250201770
    Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.
    Type: Application
    Filed: March 4, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, An-Jhih Su, Szu-Wei Lu
  • Publication number: 20250183237
    Abstract: A package structure includes a lower package including a first semiconductor die including a backside metal film on a backside of the first semiconductor die, an upper package attached to the lower package and electrically coupled to the lower package, and a thermally conductive underfill layer between the lower package and the upper package and contacting the backside metal film.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 5, 2025
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20250174510
    Abstract: A package structure and a formation method are provided. The method includes disposing a chip-containing structure over a substrate. The method also includes attaching a heat dissipation structure to the substrate through an adhesive structure. The heat dissipation structure, the substrate, and the adhesive structure together surround a first space containing the chip-containing structure. The adhesive structure has a through-hole connecting the first space to a second space outside of the first space.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 29, 2025
    Inventors: Ping-Yin HSIEH, Yi Wen HUANG, Yi-Huan LIAO, Chih-Hao CHEN, Li-Hui CHENG
  • Patent number: 12300574
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Publication number: 20250149401
    Abstract: A manufacturing method of a package structure includes: forming a first package component, where the first package component includes a first insulating encapsulation laterally covering semiconductor dies and a redistribution structure formed on the first insulating encapsulation and the semiconductor dies; coupling the first package component to a second package component; forming an underfill layer between the first and second package component, where the underfill layer extends to cover a sidewall of the first package component; forming a metallic layer on opposing surfaces of the semiconductor dies and the first insulating encapsulation by using a jig, where a window of the jig accessibly exposes the opposing surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the opposing surface of the first insulating encapsulation is shielded by the jig.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Publication number: 20250140768
    Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Application
    Filed: December 29, 2024
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12278162
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 12266633
    Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, An-Jhih Su, Szu-Wei Lu
  • Publication number: 20250105086
    Abstract: Various embodiments include integrated circuit packages and methods of forming integrated circuit packages. In an embodiment, a device includes: a package substrate; an integrated circuit device attached to the package substrate; a stiffener ring around the integrated circuit device and attached to the package substrate; a lid attached to the stiffener ring; a channel connected to an area between the lid and the integrated circuit device, the channel extending along at least one side of the integrated circuit device in a top-down view; and a thermal interface material in the channel and in the area between the lid and the integrated circuit device.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Inventors: Chun-Yen Lan, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Publication number: 20250096062
    Abstract: A package structure includes a package substrate, an interposer module on the package substrate, a thermal interface material (TIM) layer on the interposer module, and a package lid on the TIM layer, including a package lid foot portion attached to the package substrate, a package lid plate portion connected to the package lid foot portion, and a plurality of fins extending from the package lid plate portion into the TIM layer over the interposer module.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Li-Hui Cheng, Ying-Ching Shih
  • Patent number: 12237291
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 12230609
    Abstract: A semiconductor package includes a first semiconductor die, an adhesive layer, a second semiconductor die, a plurality of conductive pillars and an encapsulant. The adhesive layer is adhered to the first semiconductor die. The second semiconductor die is stacked over the first semiconductor die. The conductive pillars surround the first semiconductor die. The encapsulant encapsulates the first semiconductor die and the conductive pillars, wherein a top surface of the encapsulant is higher than top surfaces of the conductive pillars.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20250054900
    Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yen Lan, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Yu-Wei Lin
  • Publication number: 20250054824
    Abstract: A package structure including a packaging substrate, a semiconductor device, passive components, a lid, and a dam structure is provided. The semiconductor device is disposed on and electrically connected to the packaging substrate. The passive components are disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components. The lid is disposed on the packaging substrate, and the lid covers the semiconductor device and the passive components. The dam structure is disposed between the packaging substrate and the lid, wherein the dam structure covers the passive components and laterally encloses the semiconductor device.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Wen Huang, Chih-Hao Chen, Ping-Yin Hsieh, Yi-Huan Liao, Li-Hui Cheng
  • Patent number: 12224224
    Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Patent number: 12218117
    Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu