Patents by Inventor Li-Hui Cheng
Li-Hui Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942403Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.Type: GrantFiled: November 4, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
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Publication number: 20240096732Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.Type: ApplicationFiled: January 13, 2023Publication date: March 21, 2024Inventors: Chih-Hao CHEN, Li-Hui CHENG, Ying-Ching SHIH
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Publication number: 20240079399Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11923259Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.Type: GrantFiled: November 11, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
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Publication number: 20240071847Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
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Publication number: 20240071857Abstract: A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
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Patent number: 11901255Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.Type: GrantFiled: July 20, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11894287Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.Type: GrantFiled: March 10, 2023Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
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Publication number: 20240038623Abstract: In an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. The device also includes a back-side metal layer on a back-side of the package component. The device also includes an indium thermal interface material on a back-side of the back-side metal layer. The device also includes a lid on a back-side of the indium thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.Type: ApplicationFiled: July 28, 2022Publication date: February 1, 2024Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Yi-Huan Liao, Pu Wang, Li-Hui Cheng
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Publication number: 20240014100Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.Type: ApplicationFiled: August 7, 2023Publication date: January 11, 2024Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11869822Abstract: A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films. The plurality of semiconductor devices mounted on the redistribution structure. The plurality of heat dissipation films are respectively disposed on and jointly covering upper surfaces of the plurality of semiconductor devices. A plurality of trenches are respectively extended between each two of the plurality of heat dissipations and extended between each two of the plurality of semiconductor devices.Type: GrantFiled: July 23, 2021Date of Patent: January 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
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Patent number: 11855054Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.Type: GrantFiled: April 10, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11855003Abstract: A method of fabricating an integrated fan-out package is provided. A ring-shaped dummy die and a group of integrated circuit dies are mounted over a carrier, wherein the group of integrated circuit dies are surrounded by the ring-shaped dummy die. The ring-shaped dummy die and the group of integrated circuit dies over the carrier are encapsulated with an insulating encapsulation. A redistribution circuit structure is formed on the ring-shaped dummy die, the group of integrated circuit dies and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the group of integrated circuit dies, and the ring-shaped dummy die is electrically floating.Type: GrantFiled: May 13, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Hsien-Ju Tsou
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Patent number: 11830821Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.Type: GrantFiled: January 15, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20230378130Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.Type: ApplicationFiled: July 12, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, An-Jhih Su, Szu-Wei Lu
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Publication number: 20230378020Abstract: A method includes placing a package, which includes a first package component, a second package component, and an encapsulant encapsulating the first package component and the second package component therein. The method further includes attaching a first thermal interface material over the first package component, attaching a second thermal interface material different from the first thermal interface material over the second package component, and attaching a heat sink over both of the first thermal interface material and the second thermal interface material.Type: ApplicationFiled: August 8, 2023Publication date: November 23, 2023Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20230378017Abstract: An embodiment is a device including a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a first side of the package component. The device also includes a metal layer on a second side of the package component, the second side being opposite the first side. The device also includes a thermal interface material on the metal layer. The device also includes a lid on the thermal interface material. The device also includes a retaining structure on sidewalls of the package component and the thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.Type: ApplicationFiled: August 19, 2022Publication date: November 23, 2023Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Hung-Yu Chen
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Publication number: 20230369283Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20230360995Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11804468Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.Type: GrantFiled: January 15, 2021Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu