Patents by Inventor Li-Hui Lu
Li-Hui Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973005Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.Type: GrantFiled: August 3, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11942403Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.Type: GrantFiled: November 4, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
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Publication number: 20240079399Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11923259Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.Type: GrantFiled: November 11, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
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Patent number: 11335648Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.Type: GrantFiled: November 27, 2019Date of Patent: May 17, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
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Patent number: 10950525Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.Type: GrantFiled: September 3, 2019Date of Patent: March 16, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
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Publication number: 20200098704Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.Type: ApplicationFiled: November 27, 2019Publication date: March 26, 2020Inventors: Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
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Patent number: 10522479Abstract: A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.Type: GrantFiled: May 21, 2018Date of Patent: December 31, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
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Publication number: 20190393134Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.Type: ApplicationFiled: September 3, 2019Publication date: December 26, 2019Inventors: Li Zhong JIN, Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
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Patent number: 10446474Abstract: A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.Type: GrantFiled: December 21, 2017Date of Patent: October 15, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
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Publication number: 20180337143Abstract: A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.Type: ApplicationFiled: May 21, 2018Publication date: November 22, 2018Inventors: Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
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Publication number: 20180182690Abstract: A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.Type: ApplicationFiled: December 21, 2017Publication date: June 28, 2018Inventors: Li Zhong JIN, Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
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Patent number: 7767844Abstract: The present invention at first prepares a penta-alkyl DTPA and then processes a regioselective hydrolysis over the penta-alkyl DTPA while using a metal ion as a catalyst to obtain a tetra-alkyl DTPA, where, by the above two steps, a monoreactive DTPA derivative is manufactured.Type: GrantFiled: May 23, 2005Date of Patent: August 3, 2010Assignee: Atomic Energy CouncilInventors: Te-Wei Lee, Chia-Hsi Yang, Yen-Sheng Ho, Li-Hui Lu, Shu-Ling Chen
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Publication number: 20080237157Abstract: A wafer transport system is provided including providing a wafer cassette having a slot, and placing a protection insert into the slot.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Chee Keong Chin, Wen Bin Liu, Li Hui Lu
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Publication number: 20080229001Abstract: A solid memory module with extensible capacity includes at least a non-volatile memory module, each of which has at least a memory chip and a first connector, and at least a second connector, which electrically connects the first connector of the volatile memory module, at least a control unit and as a system interface. This control unit obtains external signals by this system interface and then transmits to this non-volatile memory module by the control unit to store or use the memory content.Type: ApplicationFiled: May 4, 2007Publication date: September 18, 2008Inventors: Li Hui Lu, Kun Lin Liu
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Publication number: 20080228994Abstract: A solid memory module structure with extensible capacity includes at least a non-volatile memory module, each of which has at least a memory chip, a first connector, and a control unit. And A Solid memory module includes at least a second connector, which electrically connects the first connector of the volatile memory module, and a system interfac3. The control unit of the non-volatile memory module obtains external signals by this system interface and then transmits to this non-volatile memory module by the control unit to store or use the memory content.Type: ApplicationFiled: May 4, 2007Publication date: September 18, 2008Inventors: Li Hui Lu, Kun Lin Liu
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Publication number: 20080224199Abstract: A non-volatile memory module package capability of replacing, it may connected to a solid memory module, which includes a control unit, a system interface, and a first connector, the control unit may obtains external signals by the system interface, and then transmitted to this non-volatile memory module by the control unit to store or use the memory content. The package includes a substrate; a second connector is arranged on the substrate for inserting the first connector of the solid memory module; at least a non-volatile memory chip located on the substrate, and electrically connected the substrate and the second connector; at least a passive component is arranged on the substrate; and a compound resin is covered on the non-volatile memory chip and passive component.Type: ApplicationFiled: May 4, 2007Publication date: September 18, 2008Inventors: Li Hui Lu, Kun Lin Liu, Chih Chieh Ho, Jin Xian Lin
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Publication number: 20060264669Abstract: The present invention at first prepares a penta-alkyl DTPA and then processes a regioselective hydrolysis over the penta-alkyl DTPA while using a metal ion as a catalyst to obtain a tetra-alkyl DTPA, where, by the above two steps, a monoreactive DTPA derivative is manufactured.Type: ApplicationFiled: May 23, 2005Publication date: November 23, 2006Inventors: Te-Wei Lee, Chia-Hsi Yang, Yen-Sheng Ho, Li-Hui Lu, Shu-Ling Chen