Abstract: A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.

Abstract: A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.

Abstract: A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.

Abstract: A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.

Abstract: The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.