Patents by Inventor Li Jen Choi

Li Jen Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193467
    Abstract: In a described example, an integrated circuit (IC) includes a metal oxide semiconductor (MOS) transistor formed in a semiconductor substrate. The transistor includes a gate structure formed over a surface of the substrate and source and drain regions having a first conductivity type formed in the substrate on both sides of the gate structure. A well region having a second opposite conductivity type is between the source and drain regions under the gate structure. The well region includes a well dopant and a through-gate co-implant species. The well dopant and the co-implant species have a retrograde profile extending from the surface of the substrate into the well region.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 24, 2021
    Inventors: MAHALINGAM NANDAKUMAR, BRIAN EDWARD HORNUNG, LI JEN CHOI
  • Patent number: 10720488
    Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mattias Erik Dahlström, Li Jen Choi
  • Publication number: 20190172901
    Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
    Type: Application
    Filed: January 22, 2019
    Publication date: June 6, 2019
    Inventors: Mattias Erik Dahlström, Li Jen Choi
  • Patent number: 10229966
    Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mattias Erik Dahlström, Li Jen Choi
  • Publication number: 20180190753
    Abstract: Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure.
    Type: Application
    Filed: January 30, 2017
    Publication date: July 5, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Mattias Erik Dahlström, Li Jen Choi
  • Patent number: 9041149
    Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: May 26, 2015
    Assignee: NXP, B.V.
    Inventors: Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
  • Patent number: 8373236
    Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 12, 2013
    Assignees: NXP, B.V., Interuniversitair Microelektronica Centrum VZW
    Inventors: Erwin Hijzen, Joost Melai, Wibo Van Noort, Johannes Donkers, Philippe Meunier-Beillard, Andreas M. Piontek, Li Jen Choi, Stefaan Van Huylenbroeck
  • Publication number: 20110198671
    Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.
    Type: Application
    Filed: August 5, 2009
    Publication date: August 18, 2011
    Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
    Inventors: Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
  • Publication number: 20090166753
    Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.
    Type: Application
    Filed: June 12, 2007
    Publication date: July 2, 2009
    Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
    Inventors: Erwin Hijzen, Joost Melai, Wibo D. Van Noort, Johannes J.T.M Donkers, Philippe Meunier-Beillard, Andreas M. Piontek, Li Jen Choi, Stefaan Van Huylenbroeck