Abstract: A high voltage device for an electrostatic discharge protection circuit is provided. A silicon layer is disposed in a substrate. A first type well and a second type well are disposed in the silicon layer. A lightly doped region of a second type well is located next to the first type well. A heavily doped region of the second type well is located underneath a portion of the first type well and the lightly doped region. A gate structure is disposed over a portion of the first type well and the lightly doped region. A second type first doped region and a second type second doped region are disposed in the lightly doped region and the first type well on each side of the gate structure. An isolation structure is disposed in the lightly doped region. A first type doped region is disposed in the first type well.

Abstract: A high voltage device for an electrostatic discharge protection circuit is provided. A silicon layer is disposed in a substrate. A first type well and a second type well are disposed in the silicon layer. A lightly doped region of a second type well is located next to the first type well. A heavily doped region of the second type well is located underneath a portion of the first type well and the lightly doped region. A gate structure is disposed over a portion of the first type well and the lightly doped region. A second type first doped region and a second type second doped region are disposed in the lightly doped region and the first type well on each side of the gate structure. An isolation structure is disposed in the lightly doped region. A first type doped region is disposed in the first type well.

Abstract: A process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions. After a gate is formed on the substrate on which an N well region and a P well region are separated from each other by shallow trench isolation, a silicon nitride is formed as a diffusion source layer. Subsequently, a P type ion implantation is performed in the N well region by using boron ions to form a P type diffusion source layer in the N well region. An N type ion implantation is performed in the diffusion source layer of the P well region by using arsenic ions to form a N type diffusion source layer on the P well region. Spacers are formed at the sidewalls of the gate by deposition and etching back. Heavy ion implantation is performed in the N well region and the P well region, respectively. Finally, a rapid thermal process is carried out to form a source/drain region and ultra shallow junctions in the complementary metal oxide semiconductor device.

Abstract: A semiconductor substrate having an n-well region, a p-well region and shallow trench isolation (STI ) regions is provided. And Poly-gates are formed over the n-well region and p-well region respectively. First, nitrogen oxide (such as NO, N2O) layer are formed on surface of the foresaid structure by furnace or rapid thermal oxidation (RTO). A photoresist layer is formed over the p-well region, and then BF2 or boron ion implantation is carried out to form a nitrogen oxide (such as NO, N2O) layer having boron ion in the n-well region. Another photoresist layer is formed over the n-well region after removing the photoresist layer. And then, Arsenic ion implantation is carried out to form a nitrogen oxide (such as NO, N2O) layer having Arsenic ion in the p-well region. Next, spacer is formed on the sidewall of gates after removing the photoresist layer. Finally, deep source/drain implantation are carried out once again.

Abstract: A process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions. After a gate is formed on the substrate on which an N well region and a P well region are separated from each other by shallow trench isolation, a silicon nitride is formed as a diffusion source layer. Subsequently, a P type ion implantation is performed in the N well region by using boron ions to form a P type diffusion source layer in the N well region. An N type ion implantation is performed in the diffusion source layer of the P well region by using arsenic ions to form a N type diffusion source layer on the P well region. Spacers are formed at the sidewalls of the gate by deposition and etching back. Heavy ion implantation is performed in the N well region and the P well region, respectively. Finally, a rapid thermal process is carried out to form a source/drain region and ultra shallow junctions in the complementary metal oxide semiconductor device.

Abstract: A semiconductor substrate having an n-well region, a p-well region and shallow trench isolation (STI) regions is provided. Poly-gates are formed over the n-well region and p-well region respectively. First, nitrogen oxide (such as NO, N2O) layer are formed on surface of the aforesaid structure by furnace or rapid thermal oxidation (RTO). A photoresist layer is formed over the p-well region, and then BF2 or boron ion implantation is carried out to form a nitrogen oxide (such as NO, N2O) layer having boron ion in the n-well region. Another photoresist layer is formed over the n-well region after removing the photoresist layer. Arsenic ion implantation is then carried out to form a nitrogen oxide (such as NO, N2O) layer having arsenic ion in the p-well region. Next, spacer is formed on the sidewall of gates after removing the photoresist layer. Finally, deep source/drain implantation are carried out once again.