Patents by Inventor Li-Jung LIU
Li-Jung LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103378Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system including a radiation source and an EUV control system integrated with the radiation source. The EUV control system includes a 3-dimensional diagnostic module (3DDM) designed to collect a laser beam profile of a laser beam from the radiation source in a 3-dimensional (3D) mode, an analysis module designed to analyze the laser beam profile, a database designed to store the laser beam profile, and an EUV control module designed to adjust the radiation source. The analysis module is coupled with the database and the EUV control module. The database is coupled with the 3DDM and the analysis module. The EUV control module is coupled with the analysis module and the radiation source.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Tai-Yu CHEN, Tzu-Jung PAN, Kuan-Hung CHEN, Sheng-Kang YU, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
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Publication number: 20240087947Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.Type: ApplicationFiled: January 10, 2023Publication date: March 14, 2024Inventors: Chung-Ting Ko, Yu-Cheng Shiau, Li-Jung Kuo, Sung-En Lin, Kuo-Chin Liu
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Publication number: 20240021614Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.Type: ApplicationFiled: August 4, 2023Publication date: January 18, 2024Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
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Patent number: 11830875Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.Type: GrantFiled: May 24, 2022Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
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Publication number: 20230352482Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.Type: ApplicationFiled: July 7, 2023Publication date: November 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Feng TENG, Wei-Cheng WU, Harry-Hak-Lay CHUANG, Li-Jung LIU
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Patent number: 11742348Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.Type: GrantFiled: February 24, 2021Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Feng Teng, Wei-Cheng Wu, Harry-Hak-Lay Chuang, Li-Jung Liu
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Publication number: 20220285344Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
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Publication number: 20220271031Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.Type: ApplicationFiled: February 24, 2021Publication date: August 25, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Feng TENG, Wei-Cheng WU, Harry-Hak-Lay CHUANG, Li-Jung LIU
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Patent number: 11355493Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.Type: GrantFiled: April 27, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
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Publication number: 20210288048Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.Type: ApplicationFiled: April 27, 2020Publication date: September 16, 2021Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
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Patent number: 11043385Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.Type: GrantFiled: September 4, 2020Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
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Publication number: 20200402803Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
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Patent number: 10770299Abstract: A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.Type: GrantFiled: December 23, 2019Date of Patent: September 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
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Publication number: 20200135477Abstract: A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
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Patent number: 10515811Abstract: A semiconductor device includes a semiconductor substrate, a filling conductor, an N-work function conductor layer and a gate dielectric layer. The filling conductor is over the semiconductor substrate. The N-work function conductor layer wraps around the filling conductor. The N-work function conductor layer comprises chlorine. The gate dielectric layer is between the N-work function conductor layer and the semiconductor.Type: GrantFiled: June 29, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang
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Patent number: 10262878Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: GrantFiled: October 9, 2018Date of Patent: April 16, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung Liu, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20190051542Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: ApplicationFiled: October 9, 2018Publication date: February 14, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung LIU, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
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Publication number: 20180323303Abstract: A semiconductor device includes a semiconductor substrate, a filling conductor, an N-work function conductor layer and a gate dielectric layer. The filling conductor is over the semiconductor substrate. The N-work function conductor layer wraps around the filling conductor. The N-work function conductor layer comprises chlorine. The gate dielectric layer is between the N-work function conductor layer and the semiconductor.Type: ApplicationFiled: June 29, 2018Publication date: November 8, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung LIU, Chun-Sheng LIANG, Shu-Hui WANG
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Patent number: 10109507Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.Type: GrantFiled: May 31, 2017Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Jung Liu, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
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Patent number: 10043910Abstract: A semiconductor device includes a semiconductor substrate, a plurality of gate spacers and a gate stack. The gate spacers are over the semiconductor substrate. The gate stack is over the semiconductor substrate and between the gate spacers. The gate stack includes a carbon-containing titanium nitride layer and an N-work function conductor layer over the carbon-containing titanium nitride layer.Type: GrantFiled: April 26, 2017Date of Patent: August 7, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Jung Liu, Chun-Sheng Liang, Shu-Hui Wang