Abstract: A memory array for computing-in-memory (CIM) is disclosed. The memory array for CIM includes a bit cell array, at least one word line and at least one bit line. The bit cell array has a plurality of bit cells, wherein each bit cell is operated at an operating voltage. The at least one word line is electrically connected to the bit cell array, wherein the at least one word line is associated with a first parameter. The at least one bit line is electrically connected to the bit cell array, wherein the bit cells extend along a specific direction, each the at least one bit line has an electrical parameter associated therewith, each the bit cell is associated with a second parameter, a first quantity of the plurality of bit cells of the bit cell array extends along the specific direction, and the memory array determines how an expansion associated with at least one of the first parameter and the second parameter is according to the specific direction.

Abstract: A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode.

Abstract: A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode.

Abstract: A method for manufacturing a substrate of a TFT LCD device is disclosed with following steps: providing a transparent substrate having a thin film transistors area and a storing capacitor area; forming an aluminum metal layer and a metal protecting layer on the substrate; patterning a first pattern on the aluminum metal layer of the TFT area, and a second pattern on the metal protecting layer of the storing capacitor area through a halftone mask; forming an aluminum nitride layer on the patterned metal protecting layer; removing the aluminum nitride layer form a rugged surface; forming patterned gates, patterned sources, and patterned drains over the patterned metal protecting layer of the TFT area, and forming a second metal layer over the rugged surface of the aluminum layer on the storing capacitor area, wherein the second metal layer is electrically connected with the drains; and forming patterned pixel electrodes.

Abstract: A method for manufacturing a substrate of a TFT LCD device is disclosed with following steps: providing a transparent substrate having a thin film transistors area and a storing capacitor area; forming an aluminum metal layer and a metal protecting layer on the substrate; patterning a first pattern on the aluminum metal layer of the TFT area, and a second pattern on the metal protecting layer of the storing capacitor area through a halftone mask; forming an aluminum nitride layer on the patterned metal protecting layer; removing the aluminum nitride layer form a rugged surface; forming patterned gates, patterned sources, and patterned drains over the patterned metal protecting layer of the TFT area, and forming a second metal layer over the rugged surface of the aluminum layer on the storing capacitor area, wherein the second metal layer is electrically connected with the drains; and forming patterned pixel electrodes.

Abstract: A method for manufacturing a substrate of a TFT LCD device is disclosed with following steps: providing a transparent substrate having a thin film transistors area and a storing capacitor area; forming an aluminum metal layer and a metal protecting layer on the substrate; patterning a first pattern on the aluminum metal layer of the TFT area, and a second pattern on the metal protecting layer of the storing capacitor area through a halftone mask; forming an aluminum nitride layer on the patterned metal protecting layer; removing the aluminum nitride layer form a rugged surface; forming patterned gates, patterned sources, and patterned drains over the patterned metal protecting layer of the TFT area, and forming a second metal layer over the rugged surface of the aluminum layer on the storing capacitor area, wherein the second metal layer is electrically connected with the drains; and forming patterned pixel electrodes.

Abstract: A method for manufacturing a substrate of a TFT LCD device is disclosed with following steps: providing a transparent substrate having a thin film transistors area and a storing capacitor area; forming an aluminum metal layer and a metal protecting layer on the substrate; patterning a first pattern on the aluminum metal layer of the TFT area, and a second pattern on the metal protecting layer of the storing capacitor area through a halftone mask; forming an aluminum nitride layer on the patterned metal protecting layer; removing the aluminum nitride layer form a rugged surface; forming patterned gates, patterned sources, and patterned drains over the patterned metal protecting layer of the TFT area, and forming a second metal layer over the rugged surface of the aluminum layer on the storing capacitor area, wherein the second metal layer is electrically connected with the drains; and forming patterned pixel electrodes.