Patents by Inventor Li-Li Su

Li-Li Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855188
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Chang, Ming-Hua Yu, Li-Li Su
  • Publication number: 20230395434
    Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Inventors: Bo-Yu Lai, Jyun-Chih Lin, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin, Wei Hao Lu, Li-Li Su
  • Publication number: 20230377989
    Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Hui-Lin Huang, Li-Li Su, Yee-Chia Yeo, Chii-Horng Li
  • Publication number: 20230378176
    Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
  • Publication number: 20230369502
    Abstract: A semiconductor device including a seeding layer in the source/drain region and a method of forming is provided. The semiconductor device may include a plurality of nanostructures over a substrate, a gate wrapping around the plurality of nanostructures, a source/drain region adjacent the plurality of nanostructures, and inner spacers between the source/drain region and the gate stack. The source/drain region may include a polycrystalline seeding layer covering sidewalls of the plurality of nanostructures and sidewalls of the inner spacers, and a semiconductor layer over the seeding layer. The semiconductor layer may have a higher dopant concentration than the seeding layer.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Shao-Yang Ma, Cheng-Yen Wen, Li-Li Su, Chil-Horng Li, Yee-Chia Yeo
  • Patent number: 11804487
    Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with a top surface of an STI region.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Hao Lu, Yi-Fang Pai, Cheng-Wen Cheng, Li-Li Su, Chien-I Kuo
  • Publication number: 20230343855
    Abstract: A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 26, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao LU, Chien-I KUO, Li-Li SU, Wei-Yang LEE, Yee-Chia YEO
  • Publication number: 20230343635
    Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
  • Publication number: 20230343819
    Abstract: Provided is an epitaxial structure and a method for forming such a structure. The method includes forming a fin structure on a substrate, wherein the fin structure includes a semiconductor material having substantially a {110} crystallographic orientation. The method includes etching a portion of the fin structure to expose a sidewall portion of the semiconductor material. Further, the method includes growing an epitaxial structure on the sidewall of the semiconductor material, wherein the epitaxial structure propagates with facets having a {110} crystallographic orientation.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Min Liu, Tsz-Mei Kwok, Yung-Chun Yang, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo, Hui-Lin Huang
  • Publication number: 20230317785
    Abstract: A device includes a first nanostructure over a substrate and a first source/drain region adjacent the first nanostructure. The first source/drain region includes a first epitaxial layer covering a first sidewall of the first nanostructure. The first epitaxial layer has a first concentration of a first dopant. The first epitaxial layer has a round convex profile opposite the first sidewall of the first nanostructure in a cross-sectional view. The first source/drain region further includes a second epitaxial layer covering the round convex profile of the first epitaxial layer in the cross-sectional view. The second epitaxial layer has a second concentration of the first dopant, the second concentration being different from the first concentration.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Yung-Chun Yang, Wei Hao Lu, Wei-Min Liu, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20230299180
    Abstract: The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.
    Type: Application
    Filed: May 2, 2023
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.
    Inventors: Wei-Min LIU, Yee-Chia YEO, Li-Li SU
  • Publication number: 20230275123
    Abstract: In an embodiment, a device includes: a semiconductor fin extending from a semiconductor substrate; a nanostructure above the semiconductor fin; a source/drain region adjacent a channel region of the nanostructure; a bottom spacer between the source/drain region and the semiconductor fin; and a gap between the bottom spacer and the source/drain region.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 31, 2023
    Inventors: Wei-Min Liu, Tsz-Mei Kwok, Hui-Lin Huang, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Patent number: 11728208
    Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
  • Publication number: 20230215935
    Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
    Type: Application
    Filed: March 3, 2023
    Publication date: July 6, 2023
    Inventors: Tzu-Ching Lin, Wei Te Chiang, Wei Hao Lu, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Publication number: 20230207396
    Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Inventors: Wei-Min Liu, Hsueh-Chang Sung, Li-Li Su, Yee-Chia Yeo
  • Patent number: 11688793
    Abstract: A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao Lu, Chien-I Kuo, LI-Li Su, Wei-Yang Lee, Yee-Chia Yeo
  • Publication number: 20230187524
    Abstract: A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.
    Type: Application
    Filed: May 11, 2022
    Publication date: June 15, 2023
    Inventors: Wei-Min Liu, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Patent number: 11677013
    Abstract: The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Patent number: 11600715
    Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
  • Patent number: 11600534
    Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Min Liu, Hsueh-Chang Sung, Li-Li Su, Yee-Chia Yeo