Abstract: An optimization method for an implementation of mel-frequency cepstral coefficients is provided. The optimization method includes the following steps: performing a framing step, including using a 400×16 static random access memory to temporarily store a plurality of sampling points of a sound signal with overlap, and decomposing the sound signal into a plurality of frames. Each of the plurality of frames is 400 of the sampling points, there is an overlapping region between adjacent two of the plurality of frames, and the overlapping region includes 240 of the sampling points. The optimization method further includes performing a windowing step, which includes multiplying each of the plurality of frames by a window function in a bit-level design, and the optimization method includes performing a fast Fourier transform (FFT) step, which includes applying a 512 point FFT on a frame signal to obtain a corresponding frequency spectrum.

Abstract: An optimization method for an implementation of mel-frequency cepstral coefficients is provided. The optimization method includes the following steps: performing a framing step, including using a 400×16 static random access memory to temporarily store a plurality of sampling points of a sound signal with overlap, and decomposing the sound signal into a plurality of frames. Each of the plurality of frames is 400 of the sampling points, there is an overlapping region between adjacent two of the plurality of frames, and the overlapping region includes 240 of the sampling points. The optimization method further includes performing a windowing step, which includes multiplying each of the plurality of frames by a window function in a bit-level design, and the optimization method includes performing a fast Fourier transform (FFT) step, which includes applying a 512 point FFT on a frame signal to obtain a corresponding frequency spectrum.

Abstract: A method for improving a convolutional neural network (CNN) to perform computations is provided. The method includes the following steps: determining a number of a plurality of multipliers to be N and a number of a plurality of adders to be N according to a number of convolution kernels used by a plurality of convolution layers; and in response to an i-th convolutional layer of the convolutional neural network performing a convolution operation and N convolution kernels of the i-th convolutional layer being all in a size of K×1×1, using the N multipliers and the N adders to perform a multiplication operation once and an addition operation once for each of the N convolution kernels of the i-th convolutional layer in one cycle, such that N outputs of the N convolution kernels of the i-th convolutional layer are obtained after K cycles.

Abstract: A signal transmission circuit is provided. A tri-state logic circuit includes an enabling terminal, an input terminal and an output terminal, and is conducted and unconducted when the enabling terminal is at a high and a low state respectively. A pull-up circuit pulls up a voltage level of the output terminal. A first and a second multiplexers respectively output an enabling signal and an output signal to the enabling terminal and the input terminal according to a first status of a selection signal and respectively output a high state signal according to a second status of the selection signal. A selection circuit generates the selection signal having the first status when the voltage level is not larger than a first threshold value, having the second status after the voltage level is larger than the first threshold value and having the first status afterwards.

Abstract: A signal transmission circuit is provided. A tri-state logic circuit includes an enabling terminal, an input terminal and an output terminal, and is conducted and unconducted when the enabling terminal is at a high and a low state respectively. A pull-up circuit pulls up a voltage level of the output terminal. A first and a second multiplexers respectively output an enabling signal and an output signal to the enabling terminal and the input terminal according to a first status of a selection signal and respectively output a high state signal according to a second status of the selection signal. A selection circuit generates the selection signal having the first status when the voltage level is not larger than a first threshold value, having the second status after the voltage level is larger than the first threshold value and having the first status afterwards.