Abstract: A packet buffer stores packet data of packets received by a master device. The packet buffer includes a non-guaranteed buffer, a guaranteed buffer, and a reserved buffer. The non-guaranteed buffer is visible to the master device, and is not guaranteed to provide one free cell space for one cell in a first-type packet before the non-guaranteed buffer is full. The guaranteed buffer is visible to the master device, and is guaranteed to provide one free cell space for one cell in a second-type packet before the guaranteed buffer is full. The reserved buffer is invisible to the master device, and is arranged to provide headroom for the guaranteed buffer.

Abstract: An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Abstract: A switching fabric of a network device has a load dispatcher, a plurality of store units, a storage device, a plurality of fetch units, and a load assembler. Each of the store units is used to perform a write operation upon the storage device. Each of the fetch units is used to perform a read operation upon the storage device. The load dispatcher is used to dispatch ingress traffic to the store units, wherein a data rate between the load dispatcher and each of the store units is lower than a data rate of the ingress traffic. The load assembler is used to collect outputs of the fetch units to generate egress traffic, wherein a data rate between the load assembler and each of the fetch units is lower than a data rate of the egress traffic.

Abstract: An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.

Abstract: A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.

Abstract: One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.

Abstract: An error correction device is provided. When an error of an incorrect data group stored in a memory is detected, a memory controller of the error correction device executes a burst read, burst write or burst read-modify-write (RMW) operations to the memory instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the memory.

Abstract: A method for decoding multiword information comprises steps (a) to (e). In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protective codewords are stored into a first memory, e.g., DRAM. In step (c), the high protective codewords are decoded to generate high protective word erasure indicators showing whether decoding errors occur. In step (d), the high protective word erasure indicators are stored into a second memory, e.g., SRAM. In step (e), the low protective codewords are decoded. In the meanwhile, an erasure bit for a low protective codeword is marked by finding high protective codewords close to the low protective codeword in the multiword information cluster and looking up the high protective word erasure indicators of the high protective codewords close to the low protective codeword.

Abstract: A multi-channel memory apparatus is provided. The multi-channel memory apparatus includes a host interface, storage channels, an error correcting module, and a multiple memory access module. The host interface is arranged to receive and transmit data from and to a host device. Each storage channel is coupled to a memory device for storing the data. The error correcting module is shared by the storage channels, includes an error correction code engine and a data buffer, and is arranged to perform error correction code encoding on the data to be stored into the memory devices and perform error correction code decoding on the data read out from the memory devices. The multiple memory access module is coupled between the storage channels and the error correcting module and arranged to perform multiple access control of the storage channels for the error correcting module.

Abstract: A reproduction data recording method for an optical storage medium. The method comprises storing additional data to a first temporary region of a memory device; reading the first recorded data from the optical storage medium and storing the first recorded data to the first temporary region; reading a data segment of the second recorded data from the optical storage medium and storing the data segment to a second temporary region of the memory device; reading the first recorded data from the first temporary region and the data segment from the second temporary region, and decoding the first recorded data and the data segment to confirm accuracy of the first recorded data; reading the first recorded data and the additional data from the first temporary region, and encoding the first recorded data and the additional data to generate encoded data; and writing the encoded data to the optical storage medium.

Abstract: An error correction device is provided. When an error of an incorrect data group stored in a memory is detected, a memory controller of the error correction device executes a burst read, burst write or burst read-modify-write (RMW) operations to the memory instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the memory.

Abstract: An apparatus for accessing and transferring optical data has a memory supporting the page-mode function, an accessing device used to access an error correction block from the optical storage medium and store it into the memory to make the portion of data in the same column of the error correction block stored in a particular locality greater than the portion of data in the same row of the error correction block stored in the particular locality, and an error correction decoder used to access the data of the error correction block to perform the error correction process. The apparatus uses the feature of the DRAM, such as page-mode function, and the data arrangement of the memory to improve the access efficiency of the memory. The apparatus can thus increase the access speed of the error correction decoder and improve the accessing efficiency.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.

Abstract: An exemplary storage controller for controlling data access of a storage device includes a control circuit and a soft decoder. The control circuit is utilized for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and utilized for performing a soft decoding operation upon the readout data to generate decoded data. The soft decoder may be a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder. The storage device may be a flash memory device.

Abstract: One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit.

Abstract: An error correction device is provided. When an error of a data group stored in a dynamic random access memory (DRAM) device is detected, a memory controller of the error correction device executes a burst read and write, burst write or burst read-modify-write (RMW) operations to the DRAM instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the DRAM.

Abstract: An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD) processor; a memory unit connected to the CD/DVD processor, the HDDVD processor and the BD processor to provide a storage resource; and a shared error correction code (ECC) engine for encoding or decoding the CD/DVD data stream, the HDDVD data stream and the BD data stream. Therein, the ECC engine further has a syndrome/parity generator to encode the data stream or to obtain the syndrome information from the data stream; and an erasure generator to obtain the possible error position information from the data stream. Thereby, the complexity and cost of the integrated apparatus can be reduced.

Abstract: A reproduction data recording method for an optical storage medium. The method comprises storing additional data to a first temporary region of a memory device; reading the first recorded data from the optical storage medium and storing the first recorded data to the first temporary region; reading a data segment of the second recorded data from the optical storage medium and storing the data segment to a second temporary region of the memory device; reading the first recorded data from the first temporary region and the data segment from the second temporary region, and decoding the first recorded data and the data segment to confirm accuracy of the first recorded data; reading the first recorded data and the additional data from the first temporary region, and encoding the first recorded data and the additional data to generate encoded data; and writing the encoded data to the optical storage medium.

Abstract: An embedded system for programming a programmable device including a micro controller and an I/O interface. The programmable device includes a pin set for signal delivery. The micro controller device controls the programmable device via the pin set. The I/O interface receives a program code provided externally. The micro controller executes a command sequence to program the program code into the programmable device via the pin set, and the programmable device uses the program code to provide the specific function. The command sequence may also be provided externally and sent to the micro controller via the well-known general I/O interface.