Patents by Inventor Li-Ling Liao

Li-Ling Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118178
    Abstract: A staining kit is provided, including a first pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, CD8, CD45, and CTLA4; a second pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, dendritic cell, and CD45; a third pattern including antibodies against T cell, B cell, NK cell, monocyte, CD8, CD45, CD45RA, CD62L, CD197, CX3CR1 and TCR??; and a fourth pattern including antibodies against B cell, CD23, CD38, CD40, CD45 and IgM, wherein the antibodies of each pattern are labeled with fluorescent dyes. A method of identifying characterized immune cell subsets of a disease and a method of predicting the likelihood of NPC in a subject in the need thereof using the staining kit are also provided.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 11, 2024
    Applicant: FULLHOPE BIOMEDICAL CO., LTD.
    Inventors: Jan-Mou Lee, Li-Jen Liao, Yen-Ling Chiu, Chih-Hao Fang, Kai-Yuan Chou, Pei-Hsien Liu, Cheng-Yun Lee
  • Publication number: 20240071949
    Abstract: Devices and methods for forming a chip package structure including a package substrate, a first adhesive layer attached to a top surface of the package substrate, and a beveled stiffener structure attached to the package substrate. The beveled stiffener structure may include a bottom portion including a tapered top surface, in which a bottom surface of the bottom portion is in contact with the first adhesive layer, a second adhesive layer attached to the tapered top surface, and a top portion including a tapered bottom surface, in which the tapered bottom surface is in contact with the second adhesive layer. The tapered top surface and the tapered bottom surface have a taper angle between 5 degrees and 60 degrees with respect to a top surface of the package substrate.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Li-Ling Liao, Shin-Puu Jeng
  • Publication number: 20230402404
    Abstract: Devices and method for forming a chip package structure including a package substrate, a fan-out package attached to the package substrate, a first adhesive layer attached to a top surface of the package substrate, a beveled stiffener structure attached to the package substrate and surrounding the fan-out package, the beveled stiffener structure comprising at least one tapered sidewall, in which a first width of a top portion of the beveled stiffener structure along the at least one tapered sidewall is greater than a second width of a bottom portion of the beveled stiffener structure along the at least one tapered sidewall, and in which the bottom portion is in contact with a top surface of the first adhesive layer.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Li-Ling Liao, Shin-Puu Jeng
  • Publication number: 20230395520
    Abstract: A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer. The die is electrically bonded to the interposer and disposed over the interconnection structure. The conductive terminal is connected to the interposer and the die via a conductive bump. In order to effectively avoid cold joint issues, round or rectangular polyimide structures are first disposed under the bumps to structurally support the bump and sufficiently increase bump height for improved electrical connection and long term reliability of the package structure.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Li-Ling LIAO, Ming-Chih YEW, Chia-Kuei HSU, Shin-Puu JENG
  • Publication number: 20230395515
    Abstract: Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The redistribution structure includes a first redistribution structure portion physically and electrically connected to the first semiconductor die, a second redistribution structure portion physically and electrically connected to the second semiconductor die, and a dummy bump region positioned between and electrically isolated from the first redistribution structure portion and the second redistribution structure portion.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Chin-Hua Wang, Li-Ling Liao, Shin-Puu Jeng
  • Publication number: 20230395443
    Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an interposer, a substrate, and an integrated circuit device between the interposer and the substrate. The integrated circuit device, which may correspond to an integrated passive device, is attached to the interposer within a cavity of the interposer. Attaching the integrated circuit device within the cavity of the interposer creates a clearance between the integrated circuit device and the substrate. In this way, a likelihood of the integrated circuit device contacting the substrate during a bending and/or a deformation of the semiconductor package is reduced. By reducing the likelihood of such contact, damage to the integrated circuit device and/or the substrate may be avoided to increase a reliability and/or yield of the semiconductor package.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Po-Chen LAI, Ming-Chih YEW, Li-Ling LIAO, Yu-Sheng LIN, Shin-Puu JENG
  • Publication number: 20230395492
    Abstract: A package includes a first package component, which includes a bottom dielectric layer, a micro-bump protruding below the bottom dielectric layer, and a metal pillar protruding below the bottom dielectric layer. The metal pillar has a top width and a bottom width greater than the top width. The package further includes a die underlying and bonding to the micro-bump, a solder region underlying and joining to a bottom surface of the metal pillar, and a second package component underlying the first package component. The second package component includes a conductive feature underlying and joining to the solder region.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Po-Chen Lai, Ming-Chih Yew, Li-Ling Liao, Shu-Shen Yeh, Shin-Puu Jeng
  • Publication number: 20230386988
    Abstract: Semiconductor packages and methods of fabricating semiconductor packages include bonding structures on a surface of an interposer having non-uniform height dimensions in different regions of the interposer. A plurality of solder connections may contact the pillars and electrically connect the respective pillars of the interposer to corresponding bonding structures on a package substrate. The variation in the heights of the pillars in different regions of the interposer may compensate for warping of the interposer and improve the reliability of the electrical connections between the interposer and the package substrate.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Li-Ling Liao, Ming-Chih Yew, Po-Chen Lai, Chia-Kuei Hsu, Shin-Puu Jeng, Meng-Liang Lin
  • Publication number: 20230378039
    Abstract: Some implementations herein describe a semiconductor package. The semiconductor package, which may correspond to a high-performance computing semiconductor package, includes an interposer. The interposer includes tapered interconnect structures formed using a laser plug process. The tapered interconnect structures may include a length that is lesser relative to a length of the column-shaped interconnect structures formed using a through-silicon via process. Such a length reduces a thickness of the interposer and reduces a length of electrical connections through the interposer. In this way, a signal integrity may be increased and parasitics of the semiconductor package including the tapered interconnect structures may be reduced to increase a performance of the semiconductor package. Additionally, the reduced thickness of the interposer may reduce an overall thickness of the semiconductor package to save space consumed by the semiconductor package in a computing system.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Hsien-Wei CHEN, Meng-Liang LIN, Li-Ling LIAO, Shin-Puu JENG
  • Publication number: 20230352381
    Abstract: A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Inventors: Li-Ling LIAO, Ming-Chih YEW, Chia-Kuei HSU, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20230343725
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Po-Chen LAI, Chin-Hua WANG, Ming-Chih YEW, Chia-Kuei HSU, Li-Ling LIAO, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20230326879
    Abstract: A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 12, 2023
    Inventors: Po-Chen LAI, Chin-Hua WANG, Ming-Chih YEW, Li-Ling LIAO, Tsung-Yen LEE, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20230326898
    Abstract: Devices and method for forming a chip package structure including at least one semiconductor die attached to a redistribution structure, a molding compound die frame laterally surrounding the at least one semiconductor die, and a first underfill material portion located between the redistribution structure and the at least one semiconductor die and contacting sidewalls of the at least one semiconductor die and sidewalls of the molding compound die frame. The first underfill material portion may include at least one cut region, in which the first underfill material portion may include a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230317671
    Abstract: A semiconductor structure and methods for forming the same including a package comprising at least one semiconductor die, a redistribution structure comprising bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure, a substrate package comprising chip-side bonding pads and at least one substrate trench, in which the at least one substrate trench extends vertically below a top surface of the substrate package in a cross-section view, solder material portions bonded to the chip-side bonding pads and the bonding pads, and a second underfill material portion laterally surrounding the solder material portions and dispensed within the at least one substrate trench.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Li-Ling Liao, Shin-Puu Jeng
  • Patent number: 11728284
    Abstract: A method for forming a chip package structure is provided. The method includes forming a dielectric layer over a redistribution structure. The redistribution structure includes a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The method includes forming a first conductive bump structure and a shield bump structure over the dielectric layer. The first conductive bump structure is electrically connected to the wiring layers, and the shield bump structure is electrically insulated from the wiring layers. The method includes bonding a first chip structure to the redistribution structure through the first conductive bump structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure extends across a first sidewall of the shield bump structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chen Lai, Chin-Hua Wang, Ming-Chih Yew, Chia-Kuei Hsu, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11705406
    Abstract: A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chen Lai, Chin-Hua Wang, Ming-Chih Yew, Li-Ling Liao, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230223328
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Inventors: Li-Ling Liao, Ming-Chih Yew, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11610835
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Ling Liao, Ming-Chih Yew, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230063295
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a package substrate, a first die, and a stiffener ring. The first die is disposed on the package substrate and has a first sidewall and a second sidewall opposite to each other. The stiffener ring is disposed on the package substrate to surround the first die. The stiffener ring has an inner sidewall facing the first die, and the inner sidewall at least has a slant sidewall facing the first sidewall of the first die.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Chia Yang, Shu-Shen Yeh, Li-Ling Liao, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20230066598
    Abstract: A package structure is provided. The package structure includes a redistribution structure over a substrate, a semiconductor die over the redistribution structure and electrically coupled to the substrate, and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die. The underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Po-Chen LAI, Ming-Chih YEW, Li-Ling LIAO, Chin-Hua WANG, Po-Yao LIN, Shin-Puu JENG