Patents by Inventor Li-Ling Ma

Li-Ling Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for parallel processing of IC design layouts
    Patent number: 8448096
    Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 21, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaojun Wang, Roland Ruehl, Li-Ling Ma, Mathew Koshy, Tianhao Zhang, Udayan Gumaste, Krzysztof Antoni Kozminski, Haifang Liao, Xinming Tu, Xu Zhu
  • Method and system for parallel processing of IC design layouts
    Patent number: 7657856
    Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: February 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mathew Koshy, Roland Ruehl, Min Cao, Li-Ling Ma, Eitan Cadouri, Tianhao Zhang