Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.

Abstract: A voltage regulator includes an error amplifier circuit, an output stage circuit and an output feedback path. The error amplifier circuit includes a first-stage amplifier and a second-stage amplifier. The first-stage amplifier is configured to amplify a difference between an output feedback signal and a reference signal to generate a first differential signal and a second differential signal. The second-stage amplifier is configured to amplify a difference between the first differential signal and the second differential signal to generate an output control signal. The output stage circuit is coupled with a first power terminal, and includes a switch. The switch is configured to generate an output signal at an output node according to the output control signal. The output feedback path is coupled with the output node and the error amplifier circuit, and is configured to generate the output feedback signal according to the output signal.

Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.

Abstract: The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.

Abstract: A reference-less dock and data recovery device includes a CDR circuit, an oscillator circuit, and a processor. The CDR circuit is configured to generate a first clock signal through synchronization according to a data signal having a first frequency in a first time period. The oscillator circuit is configured to output an oscillating clock signal according to the first clock signal, A frequency of the oscillating clock signal is substantially identical to that of the first clock signal. The processor oversamples the data signal having a second frequency in a second time period to generate a simulated preparation signal conforming to the second frequency. The CDR circuit is configured to generate a second clock signal through synchronization according to the simulated preparation signal. Before generating the second clock signal, the CDR circuit is synchronized to the oscillating clock signal to maintain outputting of the first clock signal.

Abstract: A circuit includes an input impedance, an operational amplifier, a voltage-adjusting circuit, a pulse-generating circuit, and a drive circuit. The input impedance is coupled to an input terminal of the operational amplifier, receives an input voltage, and outputs an input current. The operational amplifier is coupled to a first power voltage and outputs an amplified signal according to an input operating voltage and a feedback signal. The voltage-adjusting circuit adjusts the input operating voltage of the operational amplifier. The pulse-generating circuit generates a pulse width modulation signal according to the amplified signal. The drive circuit is coupled to a second power voltage and generates a driving signal according to the pulse width modulation signal. The feedback signal is correlated with the driving signal.

Abstract: A reference-less clock and data recovery device includes a CDR circuit, an oscillator circuit, and a processor. The CDR circuit is configured to generate a first clock signal through synchronization according to a data signal having a first frequency in a first time period. The oscillator circuit is configured to output an oscillating clock signal according to the first clock signal. A frequency of the oscillating clock signal is substantially identical to that of the first clock signal. The processor oversamples the data signal having a second frequency in a second time period to generate a simulated preparation signal conforming to the second frequency. The CDR circuit is configured to generate a second clock signal through synchronization according to the simulated preparation signal. Before generating the second clock signal, the CDR circuit is synchronized to the oscillating clock signal to maintain outputting of the first clock signal.

Abstract: A device is provided that includes a plurality of signal processing paths coupled in parallel, an adding circuit and an amplifier circuit. The number of the signal processing paths is N and each of the signal processing paths receives a same input signal to generate an output analog signal after a signal processing is performed, wherein each of the signal processing paths at least includes a DAC circuit and the signal processing at least includes a digital to analog conversion corresponding to the DAC circuit. The adding circuit adds the output analog signal generated from each of the signal processing paths to generate a total output analog signal. The amplifier circuit receives the total output analog signal to adjust a signal intensity of the total output analog signal according to a gain to generate an output audio signal, wherein the gain is 1/N.

Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.

Abstract: The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.

Abstract: A circuit includes an input impedance, an operational amplifier, a voltage-adjusting circuit, a pulse-generating circuit, and a drive circuit. The input impedance is coupled to an input terminal of the operational amplifier, receives an input voltage, and outputs an input current. The operational amplifier is coupled to a first power voltage and outputs an amplified signal according to an input operating voltage and a feedback signal. The voltage-adjusting circuit adjusts the input operating voltage of the operational amplifier. The pulse-generating circuit generates a pulse width modulation signal according to the amplified signal. The drive circuit is coupled to a second power voltage and generates a driving signal according to the pulse width modulation signal. The feedback signal is correlated with the driving signal.

Abstract: The present disclosure relates to a driving circuit including a first circuit, a transistor switch, and a voltage level conversion circuit. The first circuit includes an operational amplifier and a feedback circuit, and is configured to output a first signal (e.g., an analog signal). The feedback circuit is configured to feed back the first signal to the operational amplifier. A source terminal and a drain terminal of the transistor switch are respectively electrically coupled to the operational amplifier and an output pin of the driving circuit. The voltage level conversion circuit is connected to the source terminal and a gate terminal of the transistor switch. When the voltage level conversion circuit is enabled, a voltage difference between the gate terminal and the source terminal of the transistor switch is controlled to a set value, so that the first signal is output to the output pin through the transistor switch.

Abstract: A device is provided that includes a plurality of signal processing paths coupled in parallel, an adding circuit and an amplifier circuit. The number of the signal processing paths is N and each of the signal processing paths receives a same input signal to generate an output analog signal after a signal processing is performed, wherein each of the signal processing paths at least includes a DAC circuit and the signal processing at least includes a digital to analog conversion corresponding to the DAC circuit. The adding circuit adds the output analog signal generated from each of the signal processing paths to generate a total output analog signal. The amplifier circuit receives the total output analog signal to adjust a signal intensity of the total output analog signal according to a gain to generate an output audio signal, wherein the gain is 1/N.

Abstract: The present disclosure relates to a driving circuit including a first circuit, a transistor switch, and a voltage level conversion circuit. The first circuit includes an operational amplifier and a feedback circuit, and is configured to output a first signal (e.g., an analog signal). The feedback circuit is configured to feed back the first signal to the operational amplifier. A source terminal and a drain terminal of the transistor switch are respectively electrically coupled to the operational amplifier and an output pin of the driving circuit. The voltage level conversion circuit is connected to the source terminal and a gate terminal of the transistor switch. When the voltage level conversion circuit is enabled, a voltage difference between the gate terminal and the source terminal of the transistor switch is controlled to a set value, so that the first signal is output to the output pin through the transistor switch.

Abstract: A circuit including a switch and a level shift circuit is provided. The switch includes a control terminal and an input terminal. The input terminal is arranged to receive an input voltage, and the control terminal is arranged to receive a control voltage that controls a state of the switch. The level shift circuit includes a level-shifting input terminal and a level-shifting output terminal. The level-shifting input terminal is coupled to the input terminal for receiving the input voltage, and the level shift circuit is arranged to shift the input voltage to generate a shifted voltage on the level-shifting output terminal, and the control voltage is generated based on the shifted voltage.

Abstract: A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

Abstract: A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

Abstract: A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

Abstract: A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

Abstract: The present invention discloses a gain control circuit capable of easing leakage current influence. According to an embodiment of the present invention, the gain control circuit comprises: at least one signal input end for receiving at least one input signal; a signal output end for outputting an output signal; an amplifier coupled between an amplifier input end and the signal output end; and a plurality of gain schemes. Each of the gain schemes is set between the at least one signal input end and the signal output end; and when one of the gain schemes is activated to generate the output signal, the rest gain schemes are inactivated to stop gain production and concurrently discharge leakage currents through their respective grounding paths.