Abstract: A method for handling a multi-cell scheduling and a user equipment is provided. In the method, downlink control information (DCI) from a first serving cell is received. A first number of multiple scheduled cells according to the DCI is determined. The DCI is configured to schedule at least one communication on the scheduled cells. Th communication is performed on at least one of the first number of the scheduled cells according to the DCI. The DCI includes at least one single DCI field, at least one separate DCI field and at least one configurable DCI field.

Abstract: A device for handling channel access procedure includes a storage device and a processing circuit coupled to the storage device and configured to execute instructions stored in the storage device. The storage device is configured for storing the instructions of receiving an indication for an uplink transmission; determining at least one parameter of the device for a listen-before-talk procedure according to a capability of the device or a signaling from a base station; and performing the uplink transmission according to the indication.

Abstract: A UE for beam failure detection is provided. The RF signal processing device of the UE assesses a first radio link quality according to a first BFD-reference signal (BFD-RS) set including at least one reference signal, communicating with a plurality of transmission/reception points (TRPs) which include at least a first TRP and a second TRP. The processor of the UE is coupled to the RF signal processing device. When the first radio link quality is below a threshold, the processor generates a first indication, wherein the first indication is a first beam failure instance (BFI) or the first BFD-RS set. The processor enables a first timer and a first counter according to the first indication.

Abstract: A device for handling channel access procedure includes a storage device and a processing circuit coupled to the storage device and configured to execute instructions stored in the storage device. The storage device is configured for storing the instructions of receiving an indication for an uplink transmission; determining at least one parameter of the device for a listen-before-talk procedure according to a capability of the device or a signaling from a base station; and performing the uplink transmission according to the indication.

Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

Abstract: A UE for beam failure detection is provided. The UE includes a radio frequency (RF) signal processing device. The RF signal processing device receives a first candidate-beam reference-signal (RS) list and a second candidate-beam RS list and reports a beam failure information. The first candidate-beam RS list is associated with a first beam-failure-detection RS (BFD-RS) set and the second candidate-beam RS list is associated with a second BFD-RS set. The beam failure information includes at least one of following: at least on component carrier (CC) index, at least one new candidate beam, an identity of BFD-RS set, or an CORESETPoolIndex.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: This invention provides a power switch circuit and a power circuit using the power switch circuit. In particular, the power switch circuit includes a first reverse current monitoring circuit and a second reverse current monitoring circuit. The first reverse current monitoring circuit is coupled to a power transistor, and is configured to detect whether a reverse current flows through the power transistor to a voltage input terminal for a predetermined period of time, and only if yes, turn off the power transistor. The second reverse current monitoring circuit is coupled to the power transistor, and is configured to detect whether a reverse current flows through the power transistor to the voltage input terminal, and if yes, turn off the power transistor immediately.

Abstract: A multiphase converting controller, adapted to control a plural converting circuits coupled to an input voltage to commonly supply an output voltage, is disclosed. The multiphase converting controller comprises a feedback control circuit, an on-time control circuit, and a multiphase logic control circuit. The feedback control circuit determines a conduction starting point in time according to the output voltage and accordingly generates a conduction signal. The on-time control circuit determines a conduction time period. The multiphase logic control circuit controls the plural converting circuit in sequence in accordance to the conduction signal and the conduction time period. The on-time control circuit adjusts a length of the conduction time period according to a mode signal.

Abstract: This invention provides a power switch circuit and a power circuit using the power switch circuit. In particular, the power switch circuit includes a first reverse current monitoring circuit and a second reverse current monitoring circuit. The first reverse current monitoring circuit is coupled to a power transistor, and is configured to detect whether a reverse current flows through the power transistor to a voltage input terminal for a predetermined period of time, and only if yes, turn off the power transistor. The second reverse current monitoring circuit is coupled to the power transistor, and is configured to detect whether a reverse current flows through the power transistor to the voltage input terminal, and if yes, turn off the power transistor immediately. As such, the reverse current can be blocked in time from further flowing to the voltage input terminal, thereby avoiding a damage to the interior electronic components of the power source at the low voltage side.

Abstract: A power conversion apparatus including a power converter, a first output port, a second output port, a load detection circuit and an output selection circuit is provided. The power converter generates a first and a second output voltages having different voltage specification. The first and the second output ports respectively provide the received output voltages to a back end. The load detection circuit is coupled with the power converter and the second output port and detects a load requirement of a load connected to the second output port to generate a load detection signal. The power converter generates a first switch control signal according to the load detection signal to control the output selection circuit, such that the output selection circuit provides one of the first and the second output voltages in response to the first switch control signal.

Abstract: A power supply device is provided. The power supply device includes a power transistor, a detection circuit and a driving circuit. The power transistor is controlled by the driving circuit to generate an output current. A first end of the power transistor is coupled to a power voltage pin through a first bonding wire. A second end of the power transistor is configured to output the output current. The detection circuit is coupled between two ends of the first bonding wire to detect the output current and generate a control signal. The driving circuit generates a driving signal according to the control signal. When the output current value is larger than or equal to an over-current-protection current value, the driving circuit starts to adjust a voltage value of the driving signal, such that the output current value is kept at the over-current-protection current value.

Abstract: A power conversion apparatus including a power converter, a first output port, a second output port, a load detection circuit and an output selection circuit is provided. The power converter generates a first and a second output voltages having different voltage specification. The first and the second output ports respectively provide the received output voltages to a back end. The load detection circuit is coupled with the power converter and the second output port and detects a load requirement of a load connected to the second output port to generate a load detection signal. The power converter generates a first switch control signal according to the load detection signal to control the output selection circuit, such that the output selection circuit provides one of the first and the second output voltages in response to the first switch control signal.

Abstract: A zero-crossing voltage detection circuit for detecting a phase voltage of a converter includes a comparator, a first transistor and a second transistor. The first transistor has a first base, a first collector and a first emitter. The first base couples with the first collector. The first emitter receives the phase voltage. The first collector provides a first voltage to a first terminal of the comparator. The second transistor has a second base, a second collector and a second emitter. The second base couples with the first base. The second base couples with the second collector. The second emitter receives a ground voltage. The second collector provides a second voltage to a second terminal of the comparator. The comparator compares the first voltage with the second voltage to generate a zero-crossing voltage signal.

Abstract: The invention is directed to a low-dropout voltage regulator (LDO), including a power transistor, a driving stage circuit, a feedback circuit, a bias power source and an auxiliary reference current generation circuit. The power transistor is controlled by a driving signal to convert an input voltage into an output voltage. The feedback circuit generates a feedback voltage according to the output voltage. The driving stage circuit generates the driving signal according to the feedback voltage and the reference voltage. The bias power source provides a bias current. The auxiliary reference current generation circuit is configured to sample an output current, adjust the sampled output current to generate an adjustment current by means of mapping and superpose the adjustment current onto the bias current to generate a reference current to control drive capability of the driving stage circuit.

Abstract: The present invention provides a constant on time controller packaged in one single package for controlling a buck converting circuit to convert an input voltage into an output voltage. The constant on time controller includes an input voltage detecting circuit, an on-time determining circuit and a driving circuit. The input voltage detecting circuit receives a bootstrap voltage to generate an input voltage detecting signal indicative of the input voltage. The on-time determining circuit receives the input voltage detecting signal and generates an on-time signal in response to the input voltage detecting signal and the output voltage. The driving circuit controls the buck converting circuit according to the n-time signal.

Abstract: A delay circuit includes a current circuit, a first current mirror circuit, a second current mirror circuit, a self-compensation circuit, and a delay capacitor. A fixed ratio is between the first current and the second current provided by the current circuit. The first current mirror circuit generates a first mirror current in response to the first current. A partial current of the second current flowing through the second current mirror circuit is a base current, and the second current mirror circuit generates a second mirror current in response to the base current. The self-compensation circuit generates a feedback current in response to the second mirror current. The delay capacitor generates a delay signal. The charging current is equal to the second current subtracting the base current. The first mirror current is the sum of the base current, the second mirror current, and the feedback current.

Abstract: A DC-DC converter, adapted to control a converting circuit to convert an input voltage into an output voltage, is disclosed. The converting circuit comprises a switch module and an LC filter, the switch module is coupled to the input voltage, and the LC filter is coupled to the switch module and provides the output voltage. The DC-DC converter comprises a system control circuit, a driver circuit, and an output voltage adjusting circuit. The system control circuit generates a switch control signal according to a reference voltage and a state of the LC filter. The driver circuit controls the switch module according to the switch control signal for adjusting the output voltage in response to the reference voltage. The output voltage adjusting circuit determines whether adjusting the output voltage toward a predetermined adjusting voltage according to an adjusting reference voltage and a detecting voltage indicative of the output voltage.

Abstract: A feedback control circuit, adapted to control a converting circuit to transform an input power into an output voltage for driving an LED module. The feedback control circuit comprises a detection circuit, a PWM circuit, a PWM logic control circuit and a PWM control circuit. The detection circuit is coupled to at least one LED string of the LED module and generates at least one detection signal. The PWM circuit comprises a capacitance, a charging circuit and a discharging circuit, and determines a capacitance voltage of the capacitance to increase, decrease, or maintain. The PWM logic control circuit compares a level of the least one detection signal with a high reference level and a low reference level to control the PWM circuit to adjust the capacitance voltage. The PWM control circuit controls the converting circuit to execute the power transformation in response to the capacitance voltage of the capacitance.

Abstract: A buck converting controller, adapted to control a DC-DC buck converting circuit to convert an input voltage into an output voltage, is disclosed. The buck converting controller comprises a feedback control circuit, an off-time determination circuit and a load control circuit. The feedback control circuit turns on and off a high-side transistor and a low-side transistor of the DC-DC buck converting circuit in response to a feedback signal indicative of the output voltage. The off-time determination circuit determines a preset off-time period according to the input voltage and the output voltage and generates an off notice signal according to the preset off-time period. The load control circuit is coupled to the DC-DC buck converting circuit and determines whether to release an electronic energy stored in the DC-DC buck converting circuit according to the off notice signal.