Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.

Abstract: An electronic device including a display device is provided. The display device includes a sharing area, a junction area, and a privacy area. The junction area is positioned between the sharing area and the privacy area. The display device includes a privacy panel. A transmittance of the privacy panel corresponding to the sharing area is greater than a transmittance of the privacy panel corresponding to the junction area, and the transmittance of the privacy panel corresponding to the junction area is greater than a transmittance of the privacy panel corresponding to the privacy area.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: A virtual metrology method using a convolutional neural network (CNN) is provided. In this method, a dynamic time warping (DTW) algorithm is used to delete unsimilar sets of process data, and adjust the sets of process data to be of the same length, thereby enabling the CNN to be used for virtual metrology. A virtual metrology model of the embodiments of the present invention includes several CNN models and a conjecture model, in which plural inputs of the CNN model are sets of time sequence data of respective parameters, and plural outputs of the CNN models are inputs to the conjecture model.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: The disclosure relates to modified RNA molecules encoding VEGF-A polypeptides and formulations comprising the modified RNA. Aspects of the disclosure further relate to preparations and uses of formulations comprising the modified RNA in treating subjects suffering from diseases responsive to VEGF-A therapy.

Abstract: A light-emitting device, includes a semiconductor stack, including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; a first electrode formed on the first semiconductor layer, comprising a first pad electrode; a second electrode formed on the second semiconductor layer, comprising a second pad electrode and a second finger electrode extending from the second pad electrode; a second current blocking region formed under the second electrode, comprising a second core region under the second pad electrode and an extending region under the second finger electrode; and a transparent conductive layer, formed on the second semiconductor layer and covering the second core region; wherein in a top view, a contour of the second pad electrode has a circular shape and a contour of the second core region has a shape which is different from the circular shape and selected from square, rectangle, rounded rectangle, rhombus, trapezoid and polygon.

Abstract: An image processing system includes one or more processors operative to receive a graph application programming interface (API) call to add a complex node to a graph. The graph includes at least the complex node connected to other nodes by edges that are directed and acyclic. The one or more processors are further operative to process, by a graph compiler at compile time, the complex node by iteratively expanding the complex node into multiple nodes with each node corresponding to one operation in an image processing pipeline. The system further includes one or more target devices to execute executable code compiled from each node to perform operations of the image processing pipeline. The system further includes memory to store the graph compiler and the executable code.

Abstract: A graph application programming interface (API) is used to control an image processing flow. A system receives graph API calls to add nodes to respective subgraphs. The system further receives a given graph API call to add a control flow node to a main graph. The given graph API call identifies the subgraphs as parameters. The main graph includes the control flow node connected to other nodes by edges that are directed and acyclic. A graph compiler compiles the main graph and the subgraphs into corresponding executable code. At runtime, a condition is evaluated before the subgraphs identified in the given graph API call are executed. One or more target devices execute the corresponding executable code to perform operations of an image processing pipeline while skipping execution of one or more of the subgraphs depending on the condition.

Abstract: A die layout calculation method is provided. The method includes: selecting, based on a distribution array of a plurality of dies in a wafer, one die as a reference die; making first movements of a wafer center to determine a first coverage region for each first movement, and determining a feasible region based on a number of complete dies in each first coverage region; making a plurality of second movements of the wafer center in the feasible region to determine a second coverage region for each second movement, and determining a relative position of the wafer center in the reference die corresponding to a maximum number of complete dies in the second coverage region; and determining a die layout comprising a location of each die in the wafer. This method improves the accuracy and efficiency of determining the maximum number of dies.

Abstract: The invention relates to a method for ordering, sorting and/or focusing particles in a first microfluidic channel system, the method comprising the steps of i) providing for a first microfluidic channel comprising at least a first and a second inlet and a first outlet, ii) injecting a first fluid into the channel through said first inlet, iii) injecting a second fluid into the channel through said second inlet, wherein the viscosity of the first fluid is higher than the viscosity of the second fluid, such that the two fluids flow in a laminar fashion unmixed side by side, and one of the two fluids comprises the particles to be ordered, sorted and/or focused. The invention also relates to a microfluidic channel system for sorting different particles into one droplet.

Abstract: A display panel includes a first substrate and a shading structure. The shading structure is disposed on the first substrate. The shading structure includes a plurality of first parts and a second part. One of the plurality of first parts extends along a first direction. The second part protrudes from the one of the plurality of first part. Wherein the second part is separated from another one of the plurality of first parts adjacent to the one of the plurality of first parts, and the another one of the plurality of first parts extends along the first direction.

Abstract: The present disclosure provides a control method for a rectification and purification system of electronic-grade chlorine trifluoride. A rectification device of electronic-grade chlorine trifluoride includes a two-stage cryogenic rectification device including a low-boiling column and a high-boiling column. An extraction agent is arranged in the two-stage cryogenic rectification device for further dissociating associated molecules of hydrogen fluoride and chlorine trifluoride to meet the requirements of electronic-grade chlorine trifluoride. The reflux ratio parameter stability of a vapor-liquid (chlorine trifluoride-hydrogen fluoride) phase equilibrium system can be effectively improved by a column plate temperature control method, thus realizing wide dynamic smooth running under various working conditions.