Abstract: An image capture system includes a light detection and ranging (LIDAR) device which captures images of an environment while rotating and a plurality of cameras, disposed separately from the LIDAR device, each including a rolling shutter sensor and each capturing images of the environment. The plurality of cameras include a first camera disposed to face in a first direction and a second camera disposed to face in a second direction. A time at which the first camera captures a first image is synchronized with a time at which the LIDAR device captures a second image when the LIDAR device rotates to face in the first direction, and a time at which the second camera captures a third image is synchronized with a time at which the LIDAR device captures a fourth image when the LIDAR device rotates to face in the second direction.

Abstract: The present invention relates to a method, system and computer program product for task failover in an unstable environment, wherein the unstable environment includes a plurality of reclaimable nodes. According to the method, it is monitored if any node of the plurality of reclaimable nodes is to be reclaimed. Whether a task on any node of the plurality of reclaimable nodes is recoverable is determined. Responsive to the task being recoverable, data of the recoverable task is stored. Responsive to a node being reclaimed and the task on the reclaimed node being recoverable, at least one associated task of at least one associated node of the reclaimed node is notified to wait.

Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.

Abstract: A semiconductor structure includes a semiconductor substrate, an epitaxy layer, a dielectric layer, a semiconductor layer, a first semiconductor device and a second semiconductor device. The semiconductor substrate has first region and a second region. The epitaxy layer is disposed on and within the first region of the semiconductor substrate. The dielectric layer is disposed on and within the second region of the semiconductor substrate. The semiconductor layer is disposed on the dielectric layer and within the second region. The first semiconductor device is formed on the epitaxy layer. The second semiconductor device is formed on the semiconductor layer.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A header for electronic components is provided. The header has a base with at least two electrical feedthroughs each having a feedthrough pin extending through the base and being electrically isolated to the base within the feedthrough. The further includes at least one pedestal connected to the base and two submounts. Each submount includes a carrier with a structured conductor plating that has at least two conductor traces with one of the conductor traces of each submount being electrically connected to one of the feedthrough pins. The submounts are equally formed but mounted in different orientations.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A speaker includes a frame, a vibration assembly and a magnetic circuit assembly. The vibration assembly is assembled on the frame. The magnetic circuit assembly is assembled on the frame. The vibration assembly includes a voice coil and a piezoelectric element, the voice coil and the piezoelectric element are arranged coaxially, and the voice coil is between the piezoelectric element and the magnetic circuit assembly.

Abstract: Disclosed are formulations comprising SADA-complex. The formulations provide for a satisfactory shelf-life without excessive disassembly or multimerization of the SADA-complex. Further disclosed is the use of the formulation for treating cancer.

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

Abstract: A high pitch enhanced passive radiator is adapted to be utilized in a passive radiator speaker. The high pitch enhanced passive radiator includes a shell, a woofer, and the passive radiator speaker. The shell has a first slot and a second slot. The woofer is connected to the first slot. The passive radiator speaker is connected to the second slot and includes a flange, a piezoelectric speaker, and a counterweight plate. The piezoelectric speaker is connected to the flange. The projected area of the counterweight plate and the projected area of the piezoelectric speaker at least partially overlap with each other.

Abstract: A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Abstract: Embodiments of the invention provide a computer system that includes a central processing unit (CPU) associated with a host computer. The CPU includes CPU functionality and on-board enhanced CPU functionality. The CPU further includes a virtualized first instance of the CPU comprising an enabled virtualized first instance of the CPU functionality; and a non-enabled virtualized first instance of the on-chip enhanced CPU functionality. The CPU further includes a virtualized second instance of the CPU comprising an enabled virtualized second instance of the CPU functionality; and an enabled virtualized second instance of the on-chip enhanced CPU functionality.

Abstract: A method and a system for identifying a glacial lake outburst debris flow (GLODF) are provided. The method is obtained based on considering induced influences of slopes of channels and particle sizes of source particles on the GLODF. The method not only compensates for deficiencies in identifying the GLODF, but also realizes determination of the GLODF, which provides data basis for disaster prevention and control layout such as monitoring and early warning on a glacial lake and assists preventing and managing disasters caused by the GLODF. Meanwhile, multiple parameters used in the method are easy and convenient to obtain, and the parameters can be directly used on site, which saves engineering cost, improves working efficiency, and has high practical and promotional value in environmental protection and disaster prevention and mitigation.

Abstract: Embodiments relate to diagnosis and recovery of cloud based systems. From an incident ticket, a dynamic diagnostics graph is generated visualizing a hierarchy (ancestor, child) of diagnostic jobs investigating the functioning cloud system. By indicating and checking job statuses, child jobs dependent on a skipped or failed job can be skipped according to a dynamic pruning technique—thereby trimming an entire branch. And, by running separate groups of diagnostic jobs in parallel across different nodes, the diagnostic process can be finished rapidly and efficiently. A diagnostic report includes the dynamic diagnostics graph. For system recovery, the dynamic diagnostic graph is analyzed to automatically provide one or more appropriate Recommended Actions (RAs) resolving cloud system problem(s) revealed by diagnostic efforts. Those appropriate RAs may be provided by performing machine learning (e.g., referencing a neural network) with a model trained from historical cloud diagnostic and recovery activity.

Abstract: A header for an electronic component including a base body, a thermoelectric cooler, a carrier and first and second conductor track arrangements. The thermoelectric cooler is thermally attached to the base body. The carrier is coupled to the thermoelectric cooler and is cooled thereby. The first and second conductor track arrangements each have a signal conductor, at least one grounding conductor and an end. The second conductor track arrangement is on the carrier and connected to the electronic component. The first and second conductor track arrangements are separated by a gap that is bridged by bonding wire connections electrically connecting the first and second signal conductors and electrically connecting the two grounding conductors, the ends facing each other across the gap, at least one of the ends having a capacitive structural feature that increases the capacitance of the first and/or the second conductor track arrangement.

Abstract: Protection of a kernel from a sniff and code reuse attack. A kernel mode page table in initialized in a kernel. The kernel page entries in the kernel mode page table are set from s-pages to u-pages. Supervisor mode access prevention is enabled in the u-pages. Code contained in the kernel page entries in the u-pages is executed, the kernel page entries in the u-pages are capable of execution but are not capable of being accessed and read directly.