Patents by Inventor Li-Ping Wang

Li-Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950525
    Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 16, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
  • Publication number: 20200293825
    Abstract: Aspects of the present disclosure relate to automatically generating a user manual using a technique that includes training a first model with a first set of training data. The technique further includes generating, by the first model, a set of operations and a set of windows, where the set of operations and the set of windows are functions of the program. The technique further includes, generating a plurality of tasks, where a first task comprises a first operation being performed on a first window. The technique further includes determining an order of the plurality of tasks and calculating a level score for the first operation of the first window. The technique further includes assembling the user manual having the plurality of tasks in the determined order.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Xiao Feng Ji, Yuan Jin, Li ping Wang, Xiao Rui Shao
  • Publication number: 20200209196
    Abstract: A sound source device and a signal receiver are disposed at first and second ports of a target object, respectively. A sound of a specific frequency of the sound source device is introduced into the target object to generate a resonant sound wave. A computer simulates a signal generated when the resonant sound wave is received by the signal receiver and regarding the signal as reference information. The reference information comprises first data having characteristics of the resonant sound wave, and data having features of an imaginary defect formed on the target object. The features of the imaginary defect correspond to the characteristics of the resonant sound wave. When the target object has a real defect, the sound of the specific frequency of the sound source device is introduced into the target object. Features of the real defect are derived by comparing the first data with the second data.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Yao-Long Tsai, Tai-Ping Tsai, Li-Hua Wang, Yi-Tsung Pan
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10606253
    Abstract: A method of monitoring a processing system for processing a substrate is provided. The method includes the following steps: acquiring data from the processing system for a plurality of parameters, the data including a plurality of data values; grouping the parameters into a plurality of sub-groups, each of the sub-groups including a plurality of correlated parameters; constructing a principle components analysis (PCA) model from the data values for the correlated parameters in a first one of the sub-groups, including normalizing the data values in the first one of the sub-groups with a first weighting factor and a second weighting factor, wherein the first weighting factor is different from the second weighting factor; and determining a statistical quantity using the PCA model.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lian-Hua Shih, Chia-Chi Chang, Li-Ting Lin, Ching-Hsing Hsieh, Feng-Chi Chung, Meng-Chih Chang, Ming-Tung Wang, Chiu-Ping Chang, Yung-Yu Yang
  • Patent number: 10608864
    Abstract: A method of establishing a paid connection between multi-platforms, where a transmitting end application is installed in a transmitting end apparatus of a sharing source and a receiving end application is installed in a receiving end apparatus of a sharing target. When establishing a connection, the transmitting end application/receiving end application confirms whether a unique ID of the receiving end apparatus/transmitting end apparatus exists in an exception list, and confirms whether the receiving end application/transmitting end apparatus makes payment based on an operating system used by the transmitting end apparatus/receiving end application, in order to determine establishing a limited or an unlimited connection between the transmitting end apparatus and the receiving end apparatus.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 31, 2020
    Assignee: BARCO LIMITED
    Inventors: Kuo-Lung Chang, Hsing-Yung Wang, Meng-Chung Hung, Kuan-Yu Chou, Jr-Rong Fan, Shih-Ping Liu, Li-Ger Chen
  • Publication number: 20200098704
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
  • Publication number: 20200065795
    Abstract: Embodiments of the present disclosure relate to the field of network technologies, including a resource transfer method and apparatus and a storage medium. The method includes: storing a graphic code in the specified application client, the graphic code being sent by a specified server when a network is already connected, the graphic code including a user identifier used by the specified application client to log in to the specified server, and the graphic code being obtained by the specified server from a third-party server accessed by an interface of the specified server, and presenting a stored graphic code when detecting a graphic code calling operation.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Applicant: Tencent Technology (Shenzhen) Company Limited
    Inventors: Li Qiang WANG, Zhen Yu XU, Zhi Ping SU, Qi CUI, Dai Hua WANG, Nan CUI, Ru Jun ZHOU
  • Patent number: 10559573
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Patent number: 10522479
    Abstract: A method for fabricating a semiconductor structure includes forming a semiconductor chip. Forming the semiconductor chip includes providing a substrate, forming a connection layer on the substrate, and forming a first passivation layer on the substrate. The first passivation layer contains a plurality of first openings to expose the connection layer. Forming the semiconductor chip also includes forming a plurality of second openings and a plurality of third openings in the second passivation layer. Each second opening is formed in a first opening to expose the connection layer, and each third opening is formed outside of the plurality of first openings to expose the first passivation layer. Further, forming the semiconductor chip includes forming a conductive bump in each second opening.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
  • Publication number: 20190393134
    Abstract: Method for fabricating A packaging structure is provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure includes a passivation layer on the base substrate and exposing the solder pad body region and the trench region. The packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. The packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.
    Type: Application
    Filed: September 3, 2019
    Publication date: December 26, 2019
    Inventors: Li Zhong JIN, Li Hui LU, Chun Chao FEI, Po Yuan CHIANG, Ya Ping WANG
  • Patent number: 10490557
    Abstract: A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: November 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Chien-Ting Ho, Kai-Ping Chen
  • Patent number: 10446474
    Abstract: A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 15, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Li Zhong Jin, Li Hui Lu, Chun Chao Fei, Po Yuan Chiang, Ya Ping Wang
  • Publication number: 20190305311
    Abstract: The present invention relates to a battery electrode. The battery electrode comprises a plurality of carbon nanotubes and a plurality of transition metal oxide nanoparticles. The plurality of transition metal oxide nanoparticles are chemically bonded to the plurality of carbon nanotubes through carbon-oxygen-metal (C—O-M) linkages, wherein the metal being a transition metal element. The present invention also relates a method for making the battery electrode and a hybrid energy storage device using the battery electrode.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 3, 2019
    Inventors: DA-TAO WANG, LI SUN, KE WANG, JIA-PING WANG, SHOU-SHAN FAN
  • Publication number: 20190305310
    Abstract: The present invention relates to a carbon nanotube-transition metal oxide composite and a method for making the composite. The composite comprises at least one carbon nanotube and a plurality of transition metal oxide nanoparticles. The plurality of transition metal oxide nanoparticles are chemically bonded to the at least one carbon nanotube through carbon-oxygen-metal (C—O-M) linkages, wherein the metal is a transition metal element. The method for making the composite comprising the following steps: step 1, providing at least one carbon nanotube obtained from a super-aligned carbon nanotube array; step 2, pre-oxidizing the at least one carbon nanotube; step 3, dispersing the at least one carbon nanotube in a solvent to form a first suspension; step 4, dispersing a material containing transition metal oxyacid radicals in the first suspension to form a second suspension; and step 5, removing the solvent from the second suspension and drying the second suspension.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 3, 2019
    Inventors: DA-TAO WANG, LI SUN, KE WANG, JIA-PING WANG, SHOU-SHAN FAN
  • Publication number: 20190206982
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10341579
    Abstract: Embodiments are disclosed of an apparatus including a first digital camera with an image sensor optically coupled to a first lens, the first lens having a first magnification and a second digital camera including an image sensor optically coupled to a second lens. The second lens the second lens has a magnification that is greater than the magnification of the first lens and the second lens is a non-rectilinear lens having a magnification gradient in which magnification is highest at the center of the second lens and lowest at the edges. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: July 2, 2019
    Assignee: Google LLC
    Inventor: Li-Ping Wang
  • Patent number: 10292494
    Abstract: A slide rail self-return mechanism includes a holder base including a base block, a guide plate extended from the base block, a sliding groove defined in the guide plate and abutted to the base block and a mounting groove defined in the guide plate remote from the base block and disposed in communication with the sliding groove, a sliding seat slidably coupled to the holder base, and a biasing member including a body pivotally connected to the sliding seat and a position-limiting block located at the body and movable through the mounting groove into the sliding groove when the sliding seat is coupled to the holder base.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: May 21, 2019
    Assignee: Nan Jeun International Co., Ltd.
    Inventors: Kuo-Sheng Huang, Li-Ping Wang
  • Publication number: 20180367743
    Abstract: Embodiments are disclosed of an apparatus including a first digital camera with an image sensor optically coupled to a first lens, the first lens having a first magnification and a second digital camera including an image sensor optically coupled to a second lens. The second lens the second lens has a magnification that is greater than the magnification of the first lens and the second lens is a non-rectilinear lens having a magnification gradient in which magnification is highest at the center of the second lens and lowest at the edges. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 20, 2018
    Inventor: Li-Ping Wang
  • Patent number: 10108073
    Abstract: A heat transfer apparatus includes a circuit board assembly and an image sensor including a plurality of photodetectors disposed in a semiconductor material. The image sensor is mounted to the circuit board assembly. A thermal strap with a first end is thermally coupled to transfer heat out of the image sensor. A heat sink is thermally coupled to a second end of the thermal strap opposite the first end of the thermal strap to receive heat from the image sensor.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 23, 2018
    Assignee: Google LLC
    Inventors: Jerry Chiu, Katherine Stoy, Li-Ping Wang