Abstract: The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.

Abstract: Provided are a device for press-cutting glass, a method for press-cutting glass, and a glass-cutting system having the device for press-cutting glass. The device for press-cutting glass comprises a supporting member, having a first supporting portion and a second supporting portion for supporting a glass substrate, which are arranged in a spaced apart manner in a first direction; and a press-cutting member for press-cutting an edge of the glass substrate, which is positioned between the first supporting portion and the second supporting portion in the first direction. The device for press-cutting glass has advantages including high press-cutting efficiency, simple structure, low manufacturing cost, and easy assembling with other devices.

Abstract: The disclosed subject matter relates to an automated determination the stain quality and segmentation quality of a tissue sample. By way of example, separate image data is acquired of an unstained form of a biological specimen, the biological specimen stained with a nuclei marker and the biological specimen stained with a segmentation marker. A correlation map (Cr) from the separate image data and a ridgeness map (Pr) from the image data of the biological specimen stained with a segmentation marker are each determined. A staining quality score and segmentation quality score are then determined from the correlation map (Cr) and the ridgeness map (Pr).

Abstract: A method for generating an internal clock in a radio network controller and a relevant transmission processing board. The transmission processing board comprises; a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network when said transmission processing board functions as a master transmission processing board, or for obtaining a clock signal from a clock bus of a sub-rack in which said transmission processing board is located when said transmission processing board functions as a slave transmission processing board; a phase-locked loop for generating a reference transmission clock based on the clock signal extracted or obtained by said clock signal selector; and a clock driver for transmitting the generated reference transmission clock to the clock bus of the sub-rackin which said transmission processing board is located when said transmission processing board functions as a master transmission processing board.

Abstract: Device of levitation of an item over an optimized base by means of permanent magnets. The equilibrium is stable along one or two axes by means of these permanent magnets, and along the one or two others by means of a combination of electromagnets of near zero consumption at equilibrium.

Abstract: The present invention provides a method for generating an internal clock in a radio network controller and a relevant transmission processing board. The transmission processing board comprises: a clock signal selector for extracting a clock signal from a synchronous/asynchronous line connected with a core network when said transmission processing board functions as a master transmission processing board, or for obtaining a clock signal from a clock bus of a sub-rack in which said transmission processing board is located when said transmission processing board functions as a slave transmission processing board; a phase-locked loop for generating a reference transmission clock based on the clock signal extracted or obtained by said clock signal selector; and a clock driver for transmitting the generated reference transmission clock to the clock bus of the sub-rack in which said transmission processing board is located when said transmission processing board functions as a master transmission processing board.