Abstract: A novel architecture for implementing video processing features a data bus and a control bus. In an embodiment, data transfers between processing modules can take place over the data bus as mediated by a programmable memory copy controller, or through local connections, freeing up the control bus for instructions provided by a processor. A video decoder may be implemented in a system on chip with instructions provided by an off-chip processor. A semaphore or semaphore array mechanism may be used to mediate traffic between the various modules.

Abstract: This invention relates generally to hardware for scaling and filtering video data and more specifically to algorithms and techniques for accelerating scaling and filtering operations on digital video data. The hardware is designed so that scaling and filtering operations are combined and performed simultaneously where possible to speed manipulation of the video data. Efficient design of the system allows memory buffers and logic gates to be shared or eliminated to reduce the size, cost and power requirements of the hardware implementation.