Abstract: A skin layer of a superconducting tape has a woven mesh structure and is disposed on a surface of a superconducting tape. The skin layer of a superconducting tape solves the problem where a vapor layer generated when a superconductor is in a normal resistive state greatly reduces the efficiency of a heat exchange between the superconductor and liquid nitrogen. Further provided are the superconducting tape and a superconducting coil.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: A breathable and waterproof non-woven fabric is manufactured by a manufacturing method including the following steps. Performing a kneading process on 87 to 91 parts by weight of a polyester, 5 to 7 parts by weight of a water repellent, and 3 to 6 parts by weight of a flow promoter to form a mixture, in which the polyester has a melt index between 350 g/10 min and 1310 g/10 min at a temperature of 270° C., and the mixture has a melt index between 530 g/10 min and 1540 g/10 min at a temperature of 270° C. Performing a melt-blowing process on the mixture, such that the flow promoter is volatilized and a melt-blown fiber is formed, in which the melt-blown fiber has a fiber body and the water repellent disposed on the fiber body with a particle size (D90) between 350 nm and 450 nm.

Abstract: The present disclosure discloses a method for synthesizing quinolones intermediates by a continuous flow reaction. Specifically, according to the method, a microchannel reactor is used, which improves the selectivity and conversion rate of the reaction, and the conversion rate of compound ii is increased to more than 95% and the yield is increased to more than 85%; avoids the use of a solvent such as methanol, and methyl tert-butyl ether, etc., in the intermittent reaction process, which simplifies the post-processing method, shortens the overall operation time from about 24 hours to a few minutes, greatly improving the production efficiency, and realizing the continuity and automation of the whole process; and thus makes the product have high purity and high yield, which is suitable for industrial production.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.

Abstract: The present disclosure provides a packing method including following steps. Genetic algorithm is utilized to calculate multiple packing programs. Multiple candidate packing programs including all items are selected from the packing programs. Among each of the candidate packing programs, at least one of the items to be placed earlier is classified into a first subset, and at least another one of the items to be placed later is classified into a second subset. Among each of the candidate packing programs, a first packing for the first subset is maintained, and a second packing for the second subset is recalculated by using a greedy algorithm to generate an updated second packing.

Abstract: An LED display device includes a system board, and multiple daughterboards that are assembled on the system board. The system board includes a drive power circuit, a first gate circuit and a second gate circuit. Each daughterboard includes a substrate, multiple LEDs that are disposed on the substrate, multiple first transistor switches that are respectively connected to the LEDs, and at least one second transistor switch that is connected to the LEDs. With respect to each daughterboard, the first transistor switches and the at least one second transistor switch cooperatively control current flows through the LEDs; the first transistor switches are further connected to the drive power circuit to respectively receive multiple drive currents, and are further connected to the first gate circuit to receive a timing signal; and the at least one second transistor switch is further connected to the second gate circuit to receive a timing signal.

Abstract: A light emitting display device includes a substrate, a drive power circuit, a gate circuit unit, multiple LEDs and a power switch unit. The power switch unit includes multiple first transistor switches and at least one second transistor switch that cooperatively control current flows through the LEDs. The first transistor switches are respectively connected to first terminals of the LEDs. The at least one second transistor switch is connected to second terminals of the LEDs. The first transistor switches are further connected to the drive power circuit to receive multiple drive currents, and are further connected to the gate circuit unit to receive a timing input. The at least one second transistor switch is further connected to the gate circuit unit to receive a timing input. The light emitting display device can have reduced parasitic capacitance effect, and thus reduced power consumption and have improved display quality.

Abstract: A chip package and methods for fabricating the same are provided that include integrated devices embedded and coupled in series between a lower surface of a package substrate and an integrated circuit die of the chip package. In some examples, the integrated devices are disposed side by side embedded in a common package substrate. In other examples, one of the series coupled integrated devices is embedded in a first package substrate while another of the series coupled integrated devices is embedded in a second package substrate that is stacked directly in contact with the first package substrate. The integrated devices may be passive and/or active integrated devices.

Abstract: A radio frequency identification integrated circuit for reducing pin counts and an RFID providing method thereof are provided in the present invention. The radio frequency identification integrated circuit includes a first IO pin, a second IO pin and a third IO pin. The method includes determining whether the coil is coupled to the first IO pin, the second IO pin and the third IO pin when the RFID IC is enabled; and determining the identification according to the voltage status of the non-coupled pin and the pins coupled to the coil.

Abstract: Methods of preparing protein films in the presence of organofluorine compounds are provided that can produce protein films that retain the solution phase characteristics of the proteins. The protein films can be coatings for medical devices.

Abstract: The present invention belongs to the technical field of oil field drilling, and relates to a ground testing device for a stabilized platform of a rotary steerable drilling tool. The ground testing device includes: a first supporting member and a second supporting member that are oppositely arranged, where the second supporting member is provided with a first mounting hole; a drill collar and a drill collar motor mounted outside the first supporting member, where a motor shaft of the drill collar motor penetrates the first supporting member and is connected to the drill collar, and a stabilized platform mounting assembly is arranged inside the drill collar; and a first vibration member connected to the drill collar and a second vibration member arranged in the first mounting hole in a sleeved manner, where an elastic member is arranged between the second vibration member and the second supporting member, and the elastic member is arranged on the second vibration member in a sleeving manner.

Abstract: The present invention belongs to the technical field of oil field drilling, and relates to a ground testing device for a stabilized platform of a rotary steerable drilling tool. The ground testing device includes: a first supporting member and a second supporting member that are oppositely arranged, where the second supporting member is provided with a first mounting hole; a drill collar and a drill collar motor mounted outside the first supporting member, where a motor shaft of the drill collar motor penetrates the first supporting member and is connected to the drill collar, and a stabilized platform mounting assembly is arranged inside the drill collar; and a first vibration member connected to the drill collar and a second vibration member arranged in the first mounting hole in a sleeved manner, where an elastic member is arranged between the second vibration member and the second supporting member, and the elastic member is arranged on the second vibration member in a sleeving manner.

Abstract: The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

Abstract: Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.

Abstract: A chip package and method for fabricating the same are provided that includes a power delivery network (PDN) with non-uniform electrical conductance. The electrical conductance through each current path of the PDN may be selected to balance the distribution of current flow across the current paths through the chip package, thus compensating for areas of high and low current draw found in conventional designs.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.