Patents by Inventor Li-Shyue Lai
Li-Shyue Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230369107Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Li-Shyue Lai, Gao-Ming Wu, Katherine H. Chiang, Chung-Te Lin
-
Publication number: 20230138939Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer and a gate dielectric layer may be formed over the plurality of vertical stacks. Sacrificial spacers are formed around the plurality of vertical stacks. At least one dielectric wall structure may be formed around the sacrificial spacers by filling gaps between neighboring pairs of the sacrificial spacers with a dielectric fill material. The sacrificial spacers are replaced with gate electrodes. Each of the gate electrodes may laterally surround a respective row of vertical stacks that are arranged along a first horizontal direction.Type: ApplicationFiled: February 10, 2022Publication date: May 4, 2023Inventors: Gao-Ming WU, Li-Shyue LAI, Katherine H. CHIANG, Chung-Te LIN
-
Publication number: 20230038958Abstract: A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.Type: ApplicationFiled: February 11, 2022Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shyue Lai, Chien-Hao Huang, Chia-Yu Ling, Katherine H CHIANG, Chung-Te Lin
-
Publication number: 20220328346Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.Type: ApplicationFiled: June 14, 2021Publication date: October 13, 2022Inventors: Li-Shyue Lai, Gao-Ming Wu, Katherine H. Chiang, Chung-Te Lin
-
Patent number: 10861958Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.Type: GrantFiled: May 6, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Lun Cheng, Li-Shyue Lai, Ching-Wei Tsai, Kai-Chieh Yang
-
Publication number: 20190259862Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: Kuan-Lun Cheng, Li-Shyue Lai, Ching-Wei Tsai, Kai-Chieh Yang
-
Patent number: 10283623Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.Type: GrantFiled: November 14, 2017Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Lun Cheng, Li-Shyue Lai, Ching-Wei Tsai, Kai-Chieh Yang
-
Publication number: 20190035917Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.Type: ApplicationFiled: November 14, 2017Publication date: January 31, 2019Inventors: Kuan-Lun Cheng, Li-Shyue Lai, Ching-Wei Tsai, Kai-Chieh Yang
-
Patent number: 9461041Abstract: A device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.Type: GrantFiled: December 29, 2014Date of Patent: October 4, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lin Yang, Tsu-Hsiu Perng, Chih Chieh Yeh, Li-Shyue Lai
-
Publication number: 20150115372Abstract: A device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.Type: ApplicationFiled: December 29, 2014Publication date: April 30, 2015Inventors: Yu-Lin Yang, Tsu-Hsiu Perng, Chih Chieh Yeh, Li-Shyue Lai
-
Patent number: 8921218Abstract: A method and device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.Type: GrantFiled: May 18, 2012Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lin Yang, Tsu-Hsiu Perng, Chih Chieh Yeh, Li-Shyue Lai
-
Publication number: 20130307088Abstract: A method and device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Yu-Lin Yang, Tsu-Hsiu Perng, Chih Chieh Yeh, Li-Shyue Lai
-
Patent number: 8466505Abstract: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.Type: GrantFiled: March 10, 2005Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shyue Lai, Hung-Wei Chen, Wen-Chin Lee, Min-Hwa Chi
-
Patent number: 8455321Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.Type: GrantFiled: November 11, 2011Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shyue Lai, Jing-Cheng Lin
-
Patent number: 8264021Abstract: A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.Type: GrantFiled: April 16, 2010Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shyue Lai, Tsz-Mei Kwok, Chih Chieh Yeh, Clement Hsingjen Wann
-
Patent number: 8263959Abstract: A method of manufacturing a memory device is provided. The method includes forming an electrode over a substrate. The method also includes forming an opening in the electrode to provide a tapered electrode contact surface proximate the opening. The method further includes forming a phase change feature over the electrode and on the tapered electrode contact surface.Type: GrantFiled: May 9, 2007Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Hsiung Wang, Li-Shyue Lai, Denny Tang, Wen-Chin Lin
-
Patent number: 8153471Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.Type: GrantFiled: November 14, 2010Date of Patent: April 10, 2012Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Shyue Lai, Chao-Hsiung Wang, Denny Tang, Wen-Chin Lin
-
Publication number: 20120058628Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shyue Lai, Jing-Cheng Lin
-
Patent number: 8058692Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.Type: GrantFiled: December 29, 2008Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Shyue Lai, Jing-Cheng Lin
-
Patent number: 8022382Abstract: A phase change memory device and a method of forming the same are provided. The phase change memory device includes a conducting electrode in a dielectric layer, a bottom electrode over the conducting electrode, a phase change layer over the bottom electrode, and a top electrode over the phase change layer. The phase change memory device may further include a heat sink layer between the phase change layer and the top electrode. The resistivities of the bottom electrode and the top electrode are preferably greater than the resistivity of the phase change material in the crystalline state.Type: GrantFiled: March 3, 2006Date of Patent: September 20, 2011Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., Ritek CorporationInventors: Li-Shyue Lai, Denny Duan-lee Tang, Wen-chin Lin, Teng-Chien Yu, Hui-Fang Tsai, Wei-Hsiang Wang, Shyhyeu Wang