Abstract: Described herein are methods, systems, and apparatuses for detecting significantly mutated genes/pathways in a cancer cohort. A driver gene detection technique taking into account the heterogeneous mutational context in a cancer cohort is disclosed. A statistical model of a gene-specific mutation rate distribution (e.g., using an optimized gene specific mean estimation and/or a gene-specific dispersion estimation) is used to model a sample/gene-specific background mutation rate. The statistical model may then be used to detect gene/pathway enrichment and distinguish tumor suppressors and oncogenes based on the spatial distribution of non-silent mutations, loss-of-function mutations, and/or gain-of-function mutations.

Abstract: Described herein are methods, systems, and apparatuses for detecting significantly mutated genes/pathways in a cancer cohort. A driver gene detection technique taking into account the heterogeneous mutational context in a cancer cohort is disclosed. A statistical model of a gene-specific mutation rate distribution (e.g., using an optimized gene specific mean estimation and/or a gene-specific dispersion estimation) is used to model a sample/gene-specific background mutation rate. The statistical model may then be used to detect gene/pathway enrichment and distinguish tumor suppressors and oncogenes based on the spatial distribution of non-silent mutations, loss-of-function mutations, and/or gain-of-function mutations.

Abstract: A multi-lens coplanar calibration method is applicable to a three-dimensional (3D) imaging device with a plurality of lenses, and the method includes: shooting a reference surface by the 3D imaging device through the plurality of lenses to generate a plurality of 3D images, calculating a plurality of surface equations according to 3D information of the 3D images by a computing device, calculating a plurality of coordinate systems corresponding to the plurality of lenses according to the plurality of surface equations, where one of the plurality of coordinate systems is a first coordinate system, and each of the others is a second coordinate system, calculating a calibration matrix for each second coordinate system relative to the first coordinate system according to at least the plurality of coordinate systems by the computing device, and adjusting based on the calibration matrix by an actuating device.

Abstract: A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.

Abstract: A driving risk classification and prevention system for a vehicle being autonomously and manually driven, includes an orientation unit for confirming a location of the vehicle, an exterior sensing unit for sensing first information external to the vehicle, and an autonomous driving risk sensing unit for sensing second information which endanger autonomous driving of the vehicle. A communications unit is linked to the orientation unit for receiving third information corresponding to the location. A risk prevention unit is linked to the orientation unit, the exterior sensing unit, the autonomous driving risk sensing unit, and the communications unit. The risk prevention unit is used for generating a first index according to the first information, generating a second index according to the third information, generating a third index according to the second information, and determining whether a safety operation is performed according to the first index and the second index.

Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.

Abstract: A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

Abstract: Described herein are methods, systems, and apparatuses for detecting significantly mutated genes/pathways in a cancer cohort. A driver gene detection technique taking into account the heterogeneous mutational context in a cancer cohort is disclosed. A statistical model of a gene-specific mutation rate distribution (e.g., using an optimized gene specific mean estimation and/or a gene-specific dispersion estimation) is used to model a sample/gene-specific background mutation rate. The statistical model may then be used to detect gene/pathway enrichment and distinguish tumor suppressors and oncogenes based on the spatial distribution of non-silent mutations, loss-of-function mutations, and/or gain-of-function mutations.

Abstract: A warning system implemented in a vehicle includes an overspeed warning module and a display module. The overspeed warning module is configured to generate an overspeed warning signal when a speed of the vehicle exceeds a speed limit. The display module is configured to display an alerting signal perceptible by a driver when the overspeed warning signal is generated.

Abstract: A system provided for configuring settings of a device installed in a vehicle based on a user's personal attributes. The system includes an inference module that dynamically gathers one or more personal attributes of the user, and a control unit that applies a configuration to the device based on the personal attributes.

Abstract: Methods and apparatus are disclosed for assembling a motor rotor. The apparatus includes a rotor fixing module, a conductive bar driving module, a plurality of conductive bars and a pump module. The rotor fixing module supports and holds the rotor. The conductive bar driving module has a plurality of assembling slots. When the pumping module is attached to the conductive bar driving module and each of the conductive bars seals the assembling slots, the pumping module and the assembling slots cooperatively form a sealed chamber, and the pumping module vacuums the sealed chamber to generate a suction force on each of the conductive bars, and the suction force further drives the conductive bars into the assembling slots. The method is for assembling the rotor by utilizing the same procedure mentioned above.

Abstract: A warning system implemented in a vehicle includes a proximity warning module and a display module. The proximity warning module is configured to detect an object approaching the vehicle and generate a proximity warning signal. The display module is configured to display a signal in the side area when the proximity warning signal is generated, where a position of the signal is determined based on a relative direction of the object to the vehicle.

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.

Abstract: A video recording device includes an image capturing module, a storage unit and a processing unit. The image capturing module is configured to capture a raw video in a first video format. The processing unit is configured to convert video session(s) other than the lately captured video content from the first video format into a second video format. The second video format is inferior than the first video format.

Abstract: A battery cell management and balance circuit comprises multiple battery cell balance circuits, multiple battery cell monitor units, multiple battery module balance circuits and a battery management unit. The battery cell balance circuits connect to battery cells for executing a first charge or discharge command. The battery cell monitor units monitor battery cells for generating battery cell information and the first charge or discharge commands. The battery module balance circuits connect to battery modules for executing second charge or discharge commands. The battery management unit connect to the battery cell monitor units for receiving battery cell information and the battery module balance circuits for direct or indirectly generating the second charge or discharge commands to the battery module balance circuits. A battery system and a battery cell management and balance circuit method is also introduced.

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

Abstract: A battery management and balance circuit comprises multiple battery group balance circuits, multiple battery module balance circuits and a battery management unit. The battery group balance circuits connect to battery groups for executing first charge or discharge command. The battery management unit connect to the battery group balance circuits and the battery module balance circuits for generating the first and second charge or discharge commands to the battery module balance circuits. A battery system and a battery management and balance circuit method is also introduced.