Abstract: A source driver and an operation method thereof are provided. The operation method includes following steps. A data signal is provided to the source driver. The operating current of the source driver is reduced to an abnormal operating level in period from the source driver is reset to before a pixel data of the source driver is appeared in the data signal. The operation current of the source driver is restored to a normal operating level when the pixel data of the source driver is appeared in the data signal.

Abstract: A display apparatus and a driving method for the display apparatus are provided. The display apparatus includes a display panel and a first source driver. The display panel has a pixel array. The first source driver sequentially supplies a first overdrive voltage and a driving voltage to a pixel in the pixel array. The first overdrive voltage has a plurality of voltage levels according to positions of pixels in the pixel array.

Abstract: A gate driver for controlling a display apparatus is provided. The gate driver includes a logic circuit, a plurality of buffers, and a charge sharing module. The logic circuit generates a plurality of switch signals. The buffers are coupled to the logic circuit. Each of the buffers determines to provide a first voltage or a second voltage according to one of the switch signals to generate a gate driving signal. The charge sharing module is coupled to the output ends of the buffers and allows the output ends of the buffers to share charges according to a plurality of sharing signals during a forward edge and a backward edge of a square wave of each of the gate driving signals. Furthermore, a gate driving method for controlling a display apparatus is also provided.

Abstract: A display driver, which comprises: a first predetermined voltage level providing apparatus, for providing a first predetermined voltage level group comprising at least one first predetermined voltage level; a first image data providing apparatus, for outputting a first image data; and a detection controlling circuit, for determining if an output terminal of the first image data providing apparatus is pre-charged to the first predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level.

Abstract: A display driving method and an associated driving circuit are provided, where the display driving method includes: checking relationships between two voltage levels respectively represented by two continuously received digital codes received by a specific digital code input terminal and a first predetermined threshold, and preferably further checking a relationship between at least one voltage level represented by at least one digital code of the two continuously received digital codes and a first predetermined zone, in order to determine whether to pre-charge a specific set of display cells within a plurality of sets of display cells, the specific set corresponding to the specific digital code input terminal; when it is determined to pre-charge the specific set of display cells, temporarily conducting a pre-charging voltage generator to the specific set of display cells to pre-charge the specific set of display cells.

Abstract: A driving integrated circuit (IC) is disclosed. The driving IC comprises a signal processing circuit, a receiver and a terminal resistance providing circuit. The receiver is coupled to a first transmission line and a second transmission line and is output to the signal processing circuit after receiving a transmission signal through the first transmission line and the second transmission line. The terminal resistance providing circuit is coupled to the receiver.

Abstract: A flat panel display with multi-drop interfaces is disclosed. The flat panel display with multi-drop interfaces includes a plurality of driver chips having a plurality of respective hardware setting values via a hardware setting, and a timing controller for transmitting at least one signal to the plurality of driver chips via at least one multi-drop interface, wherein the timing controller and a specific driver chip among the plurality of driver chips negotiate with each other according to a corresponding specific respective hardware setting value among the plurality of respective hardware setting values.

Abstract: A data transmission device includes a data division unit for receiving an original transmission data and dividing the original transmission data into a plurality of division data; a data generation unit for generating a plurality of packet data according to the plurality of division data and a plurality of clock data, wherein each of the clock data is a multi-bit data; and a data output unit for outputting the plurality of packet data to a data reception device; where each of the packet data includes a division data and a clock data, each of the packet data corresponds to a packet data period, and the division data corresponds to a division data period of the packet data period and the clock data corresponds to a clock period of the packet data period.

Abstract: A driving method for a display device including one or more than one integrated source drivers includes generating at least a control signal, and transmitting the at least a control signal to a first integrated source driver of one or more than one integrated source drivers, so that the first integrated source driver generates at least a reference voltage according to the received control signal, wherein the at least a reference voltage is used for driving the first integrated source driver.

Abstract: A driving method applicable to a display device including multiple display driving circuits, includes: the display driving circuits synchronously receiving a start pulse and generating a synchronous timing signal; a previous display driving circuit sending out a first signal to a rear display driving circuit, so that the rear display driving circuit detects and stores a signal reception delay, the display reception delay denoting a delay between the synchronous timing signal and the first signal received by the rear display driving circuit; after storing the display reception delay, the rear display driving circuit temporarily stopping receiving a system clock signal and temporarily stopping generating the synchronous timing signal; and the previous display driving circuit sending a second X signal to the rear display driving circuit to wake up the rear display driving circuit for preparing to receive a display data.

Abstract: A gate driver for controlling a display apparatus is disclosed. The gate driver includes a logic circuit for generating a plurality of switch signals, a breaking signal and a plurality of sharing signals, a plurality of buffers, each for determining to provide a first voltage or a second voltage according to one of the plurality of switch signals to generate a gate driving signal, and a charge recycle module for sharing charges with a plurality of loads according to the plurality of sharing signals.

Abstract: A gate driver for controlling a display apparatus is provided. The gate driver includes a logic circuit, a plurality of buffers, and a charge sharing module. The logic circuit generates a plurality of switch signals. The buffers are coupled to the logic circuit. Each of the buffers determines to provide a first voltage or a second voltage according to one of the switch signals to generate a gate driving signal. The charge sharing module is coupled to the output ends of the buffers and allows the output ends of the buffers to share charges according to a plurality of sharing signals during a forward edge and a backward edge of a square wave of each of the gate driving signals. Furthermore, a gate driving method for controlling a display apparatus is also provided.

Abstract: An electronic device includes a circuit board and a heat insulating structure. The heat insulating structure includes a heat source, an enclosure for covering the heat source, and a heat insulating plate disposed on a side of the enclosure facing to the heat source for preventing heat generated by the heat source from directly transmitting toward the enclosure, and a space being formed between the heat insulating plate and the enclosure. The heat insulating structure further includes a thermal conductive layer disposed on a side of the heat insulating plate facing to the heat source. The heat insulating structure further includes the thermal conductive layer disposed on a side of the heat insulating plate facing to the enclosure. Therefore, the heat insulating plate can be for altering heat current generated by the heat source so as to dissipate the heat current via holes on the enclosure uniformly.