Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element is substantially free of oxygen. The semiconductor device structure also includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the gate stack and the spacer element. The semiconductor device structure further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate. An angle between a sidewall of the conductive contact and a top surface of the spacer element is in a range from about 90 degrees to about 120 degrees, and the conductive contact covers a portion of the spacer element.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy gate structure. The first layer further includes a top layer on an entire structure formed on a fin structure, and a gate space for a short channel gate and a gate space for a long channel gate. A first portion of the top layer is removed to leave a hard mask layer over a long channel gate region. The hard mask layer and a portion of heights of the conductive material in the gate spaces are removed to form a first structure. A second layer of the conductive material is formed over the first structure. Portions of the second layer are removed to create a recessed conductive portion for the short channel gate and a recessed conductive portion for the long channel gate.

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A semiconductor device and method of manufacture are provided in which an the physical characteristics of a dielectric material are modified in order to provide additional benefits to surrounding structures during further processing. The modification may be performed by implanting ions into the dielectric material to form a modified region. Once the ions have been implanted, further processing relies upon the modified structure of the modified region instead of the original structure.

Abstract: A method includes forming a first conductive feature in a first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer. The second dielectric layer and the etch stop layer are patterned to form an opening, where a portion of the etch stop layer is interposed between a bottom of the opening and the first conductive feature. The portion of the etch stop layer is sputtered to extend the opening toward the first conductive feature and form an extended opening, where the extended opening exposes the first conductive feature. The extended opening is filled with a conductive material to form a second conductive feature in the second dielectric layer.

Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element is substantially free of oxygen. The semiconductor device structure also includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the gate stack and the spacer element. The semiconductor device structure further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate. An angle between a sidewall of the conductive contact and a top surface of the spacer element is in a range from about 90 degrees to about 120 degrees, and the conductive contact covers a portion of the spacer element.

Abstract: A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a spacer layer and a dielectric layer over a substrate. The spacer layer has an opening exposing the substrate, and the dielectric layer surrounds the spacer layer. The method includes forming a metal silicon nitride layer over a sidewall and a bottom surface of the opening. The method includes forming a first work function metal layer over the metal silicon nitride layer. The method includes removing a first top portion of the first work function metal layer. The method includes, after the removal of the first top portion, removing a second top portion of the metal silicon nitride layer. The method includes forming a conductive layer in the opening. The method includes removing a third top portion of the conductive layer and a fourth top portion of the metal silicon nitride layer.

Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.

Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

Abstract: Disclosed is a method of fabricating an image sensor device, such as a BSI image sensor, and more particularly, a method of forming a dielectric film in a radiation-absorption region without using a conventional plasma etching causing roughness on the surface and non-uniformity within a die and a wafer. The method includes providing layers comprising a substrate having radiation sensors adjacent its front surface, an anti-reflective layer formed over the back surface of the substrate, a sacrificial dielectric layer formed over the anti-reflective layer, and a conductive layer formed over the sacrificial dielectric layer in a radiation-blocking region. The method further includes removing the sacrificial dielectric layer in the radiation-absorption region completely by a highly selective etching process and forming a dielectric film on the anti-reflective layer by deposition such as CVD or PVD while precisely controlling the thickness.

Abstract: A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a gate structure. The gate structure includes a gate electrode over a gate dielectric, the gate dielectric having a bottom surface in a first plane. A second etch interacts with a first composition and an initial dopant to remove a bottom portion of a first sidewall spacer adjacent the gate structure, such that a bottom surface of the first sidewall spacer lies in a second plane different than the first plane. The removal of the bottom portion of the first sidewall spacer reduces a first distance between a source or drain and a bottom surface of the gate electrode, thus reducing proximity loading of the semiconductor device and improving functionality of the semiconductor device.

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract: A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a gate structure. The gate structure includes a gate electrode over a gate dielectric, the gate dielectric having a bottom surface in a first plane. A second etch interacts with a first composition and an initial dopant to remove a bottom portion of a first sidewall spacer adjacent the gate structure, such that a bottom surface of the first sidewall spacer lies in a second plane different than the first plane. The removal of the bottom portion of the first sidewall spacer reduces a first distance between a source or drain and a bottom surface of the gate electrode, thus reducing proximity loading of the semiconductor device and improving functionality of the semiconductor device.