Patents by Inventor Li-Te Lin
Li-Te Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12217961Abstract: A method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process. The lateral etching process includes a radical etching process and a chemical etching process. Alternatively, the lateral etching process includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.Type: GrantFiled: July 1, 2022Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chien Kuang, Tze-Chung Lin, Li-Te Lin
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Patent number: 12218219Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.Type: GrantFiled: August 27, 2021Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Hao Chang, Fo-Ju Lin, Fang-Wei Lee, Li-Te Lin, Pinyen Lin
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Publication number: 20250040238Abstract: In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.Type: ApplicationFiled: July 28, 2023Publication date: January 30, 2025Inventors: Yu-Wei Lu, Kenichi Sano, Tze-Chung Lin, Fang-Wei Lee, Chia-Chien Kuang, Yi-Chen Lo, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
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Patent number: 12198939Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.Type: GrantFiled: June 24, 2022Date of Patent: January 14, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
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Patent number: 12183805Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: GrantFiled: May 28, 2021Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang Wu, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin, Chung-Cheng Wu, Gwan-Sin Chang, Pinyen Lin
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Publication number: 20240404860Abstract: Processing apparatuses and methods are provided. A processing apparatus includes an electrostatic chuck configured to hold a semiconductor wafer during a process performed on the semiconductor wafer; a first electrode configured to bias a first region of the electrostatic chuck with a first bias; and a second electrode configured to bias a second region of the electrostatic chuck with a second bias.Type: ApplicationFiled: June 1, 2023Publication date: December 5, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fu Kuo, Bing-Hung Chen, Li-Te Lin, Hao-Heng Liu
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Publication number: 20240395626Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Wei-Lun CHEN, Chao-Hsien HUANG, Li-Te LIN, Pinyen LIN
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Patent number: 12154969Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer. The semiconductor device structure also includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure. The topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than a topmost surface of the work function layer.Type: GrantFiled: November 22, 2021Date of Patent: November 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hao Chang, Li-Te Lin, Pinyen Lin
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Patent number: 12154970Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.Type: GrantFiled: June 30, 2022Date of Patent: November 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Chung Lin, Han-Yu Lin, Li-Te Lin, Pinyen Lin
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Publication number: 20240387693Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hao Chang, Fo-Ju Lin, Fang-Wei Lee, Li-Te Lin, Pinyen Lin
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Publication number: 20240379333Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Jung-Hao Chang, Po-Chin CHANG, Pinyen LIN, Li-Te LIN
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Publication number: 20240363395Abstract: Embodiments of the present disclosure provide a protective layer deposited over bottom structures to protect the bottom structure during fabrication of upper structures. The protective layer may prevent STI loss and bottom spacer loss during source/drain etch back process. The protective layer may also improve process uniformity by also eliminate process loading or non-uniformity in the STI loss, fin sidewall spacer height, and recess profiles. The protective layer may also slow down fin sidewall spacer etching rate during semiconductor fin etch back, thus, improving source/drain regions profile control.Type: ApplicationFiled: August 8, 2023Publication date: October 31, 2024Inventors: Chun-Fu KUO, Kuan-Da HUANG, Chao-Hsien HUANG, Li-Te LIN
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Publication number: 20240363756Abstract: A semiconductor device includes: a semiconductor fin extending along a first lateral direction; a gate structure extending along a second lateral direction perpendicular to the first lateral direction and straddling the semiconductor fin; an epitaxial structure disposed in the semiconductor fin and next to the gate structure; a first interconnect structure extending along the second lateral direction and disposed above the epitaxial structure; and a dielectric layer including a first portion and a second portion that form a stair.Type: ApplicationFiled: June 7, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Yi-Shan Chen, Kuan-Da Huang, Han-Yu Lin, Li-Te Lin, Ming-Huan Tsai
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Publication number: 20240363721Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin CHANG, Ming-Huan TSAI, Li-Te LIN, Pinyen LIN
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Patent number: 12125897Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.Type: GrantFiled: June 28, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
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Publication number: 20240347345Abstract: A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
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Publication number: 20240322010Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.Type: ApplicationFiled: June 3, 2024Publication date: September 26, 2024Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
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Publication number: 20240313116Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.Type: ApplicationFiled: May 21, 2024Publication date: September 19, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
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Patent number: 12094951Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.Type: GrantFiled: April 19, 2023Date of Patent: September 17, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin Chang, Ming-Huan Tsai, Li-Te Lin, Pinyen Lin
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Patent number: 12087558Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.Type: GrantFiled: August 13, 2021Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hao Chang, Po-Chin Chang, Pinyen Lin, Li-Te Lin