Patents by Inventor Li-Te Lin
Li-Te Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10157751Abstract: A method for manufacturing a semiconductor device, including forming a first hard mask strip, a second hard mask strip, and a dummy structure over a substrate, in which the dummy structure is formed between and in contact with the first hard mask strip and the second hard mask strip; forming a hard mask layer over the first hard mask strip, the dummy structure, and the second hard mask strip; patterning the hard mask layer to form an opening exposing the first hard mask strip and the dummy structure, and partially exposing the second hard mask strip; and performing an etching process to remove the first hard mask strip and form a recess in the second hard mask strip, in which the performing the etching process includes forming a polymer in the recess.Type: GrantFiled: October 26, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Hao Chang, Chao-Hsien Huang, Wen-Ting Lan, Shi-Ning Ju, Li-Te Lin, Kuo-Cheng Ching
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Patent number: 10157773Abstract: A method of forming a semiconductor structure is provided. In this method, a semiconductor substrate is provided. A SoC layer is formed on the semiconductor substrate. A hard mask layer is formed over the SoC layer. The hard mask layer is patterned to expose a portion of the SoC layer. At least one opening is formed on the portion of the SoC layer using an ALE operation, thereby enabling the remaining portion of the SoC layer adjacent to the at least one opening to have a re-entrant angle included between a sidewall of the SoC layer and a bottom of the SoC layer.Type: GrantFiled: November 28, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Shan Chen, Chan-Syun David Yang, Li-Te Lin, Pinyen Lin
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Publication number: 20180315602Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.Type: ApplicationFiled: August 23, 2017Publication date: November 1, 2018Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Li-Te Lin, Ru-Gun Liu, Min Cao
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Patent number: 10032887Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.Type: GrantFiled: April 17, 2017Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lien Huang, Li-Te Lin, Yuan-Hung Chiu, Han-Yu Lin
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Publication number: 20180175171Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.Type: ApplicationFiled: July 7, 2017Publication date: June 21, 2018Inventors: Yi-Chen LO, Li-Te LIN, Yu-Lien HUANG
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Publication number: 20170365691Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.Type: ApplicationFiled: April 17, 2017Publication date: December 21, 2017Inventors: Yu-Lien Huang, Li-Te Lin, Yuan-Hung Chiu, Han-Yu Lin
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Patent number: 9627258Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.Type: GrantFiled: June 15, 2016Date of Patent: April 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lien Huang, Li-Te Lin, Yuan-Hung Chiu, Han-Yu Lin
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Patent number: 7390753Abstract: A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.Type: GrantFiled: November 14, 2005Date of Patent: June 24, 2008Assignee: Taiwan Semiconductor Mfg. Co., Ltd.Inventors: Li-Te Lin, Yui Wang, Huan-Just Lin, Yuan-Hung Chiu, Hun-Jan Tao
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Patent number: 7253112Abstract: A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.Type: GrantFiled: August 10, 2004Date of Patent: August 7, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bang-Chien Ho, Jian-Hong Chen, Tsang-Jiuh Wu, Li-Te Lin, Li-Chih Chao, Hua-Tai Lin, Shyue-Sheng Lu
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Publication number: 20070148919Abstract: A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.Type: ApplicationFiled: December 22, 2005Publication date: June 28, 2007Inventors: Li-Te Lin, Pang-Yen Tsai, Chih-Chien Chang, Tze-Liang Lee
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Publication number: 20070111110Abstract: A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.Type: ApplicationFiled: November 14, 2005Publication date: May 17, 2007Inventors: Li-Te Lin, Yui Wang, Huan-Just Lin, Yuan-Hung Chiu, Hun-Jan Tao
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Publication number: 20070057287Abstract: MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.Type: ApplicationFiled: September 15, 2005Publication date: March 15, 2007Inventors: Li-Te Lin, Chih-Chien Chang, Tze-Liang Lee
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Publication number: 20060216918Abstract: The formation of gate spacers on the sides of a gate structure on a semiconductor substrate is provided. In one embodiment, a gate structure is formed on a gate insulator layer of the semiconductor substrate. A liner layer is formed over the exposed surfaces of the substrate, the gate insulator layer, and the gate structure. A layer of gate spacer material is formed over the liner layer. Thereafter, gate spacers are formed from the layer of gate spacer material. A protection layer is formed over portions of the liner layer, gate structure, and the gate spacers. The protection layer is etched back. A first wet etch procedure is performed to remove exposed portions of the liner layer. The protection layer is removed and a second wet etch procedure is performed to remove substantially a top portion and a bottom portion of the liner layer.Type: ApplicationFiled: March 22, 2005Publication date: September 28, 2006Inventors: Ju-Chien Chiang, Shu-Huei Sun, Li-Te Lin
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Patent number: 7109085Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.Type: GrantFiled: January 11, 2005Date of Patent: September 19, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shiang-Bau Wang, Li-Te Lin, Ming-Ching Chang, Ryan Chia-Jen Chen, Yuan-Hung Chiu, Hun-Jan Tao
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Publication number: 20060154487Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.Type: ApplicationFiled: January 11, 2005Publication date: July 13, 2006Inventors: Shiang-Bau Wang, Li-Te Lin, Ming-Ching Chang, Ryan Chen, Yuan-Hung Chiu, Hun-Jan Tao
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Publication number: 20050118755Abstract: A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.Type: ApplicationFiled: November 29, 2004Publication date: June 2, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te Lin, Fang-Chen Cheng, Huin-Jer Lin, Yuan-Hung Chiu, Hun-Jan Tao
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Publication number: 20050081781Abstract: A fully dry etch method is described for removing a high k dielectric layer from a substrate without damaging the substrate and has a high selectivity with respect to a gate layer. The etch is comprised of BCl3, a fluorocarbon, and an inert gas. A low RF bias power is preferred. The method can also be used to remove an interfacial layer between the substrate and the high k dielectric layer. A HfO2 etch rate of 55 Angstroms per minute is achieved without causing a recess in a silicon substrate and with an etch selectivity to polysilicon of greater than 10:1. Better STI oxide divot control is also provided by this method. The etch through the high k dielectric layer may be performed in the same etch chamber as the etch process to form a gate electrode.Type: ApplicationFiled: October 17, 2003Publication date: April 21, 2005Inventors: Huan-Just Lin, Ming-Huan Tsai, Li-Te Lin, Yuan-Hung Chiu, Han-Jan Tao
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Publication number: 20050032386Abstract: A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.Type: ApplicationFiled: August 4, 2003Publication date: February 10, 2005Inventors: Ming-Ching Chang, Li-Te Lin, Yu-I Wang, Yuan-Hung Chiu, Hui-Jan Tao
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Publication number: 20050014362Abstract: A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.Type: ApplicationFiled: August 10, 2004Publication date: January 20, 2005Inventors: Bang-Chien Ho, Jian-Hong Chen, Tsang-Jiuh Wu, Li-Te Lin, Li-Chih Chao, Hua-Tai Lin, Shyue-Sheng Lu
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Patent number: 6743732Abstract: A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast.Type: GrantFiled: January 26, 2001Date of Patent: June 1, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Li-Te Lin, Li-Chih Chao, Chia-Shiung Tsai