Abstract: A display panel and a display device are provided. The display panel comprises a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of wiring structures and a plurality of pads. The substrate comprises a display area and a non-display area comprising a bending area. The sub-pixels and data lines are in the display area and electrically connected with each other. The wiring structures are in the bending area and electrically connected with the data lines. At least one wiring structure comprises a plurality of hollow patterns connected successively, each hollow pattern comprises a first conductive part and a second conductive part connected with each other. The plurality of pads are in the non-display area and located on a side of the plurality of wiring structures away from the display area and electrically connected with the plurality of wiring structures.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

Abstract: An nGraph-based graphics processing unit (GPU) backend distributed training method and system, a computer-readable storage medium, and an electronic device. The method includes: receiving a training request, and obtaining corresponding training data; obtaining a Nvidia® Collective multi-GPU Communication Library (NCCL) file by means of a system path of the NCCL file linked to an nGraph framework; invoking an NCCL communication interface configuration according to the training request to obtain a training model, the NCCL communication interface is an NCCL file-based communication operation interface located at a GPU backend of the nGraph framework; and performing GPU backend training on the training data using the training model. The present application can satisfy an urgent need of a user for performing neural network distributed training on the basis of an nGraph GPU backend, thus further improving the performance of deep learning network training.

Abstract: Provided are a pixel circuit and a driving method therefor, and a display apparatus. The pixel circuit includes a drive transistor, a reset circuit, a data writing circuit, a storage capacitor circuit, a threshold value compensation circuit, a conduction control circuit, a light-emitting control circuit, and a light-emitting device; the conduction control circuit is configured to: conduct the threshold value compensation circuit with the gate of the drive transistor, and conduct the reset circuit with the gate of the drive transistor at the reset stage, the threshold value detecting stage and the data writing stage; and cut off a conducting state of the threshold value compensation circuit with the gate of the drive transistor, and cut off a conducting state of the reset circuit with the gate of the drive transistor at the driving stage; where the conduction control circuit includes an oxide semiconductor thin film transistor.

Abstract: An additively manufactured high-strength and high-ductility stainless steel is characterized in that the composition, by weight percentage, C?0.05 wt %, Si?1 wt %, Mn?1 wt %, Cr 14.5-15.5 wt %, Ni 5.0-5.5 wt %, Cu 4-4.5 wt %, Nb 0.35-0.45 wt %, and the balance of Fe and unavoidable impurities. And Cr equivalent of Creq=% Cr+% Mo+2.2% Ti+0.7% Nb+2.48% Al. Ni equivalent of Nieq=% Ni+35% C+20% N+0.25% Cu. The yield strength of the high-strength and high-ductility stainless steel ?1270 MPa, the tensile strength ?1380 MPa, and the elongation after fracture ?15%.

Abstract: A pulse stimulation device and method, and a medical apparatus. The device comprises an R-wave sensing module (1), a cardiac stimulation pulse generator (2) and at least one control electrode (3); the R-wave sensing module (1) is used for acquiring a surface electrocardiogram and/or a myocardial electrocardiogram, and for acquiring an R-wave sensing time of the appearance of an R wave, so as to determine a pulse delivery time for each preset stimulation position, and the pulse delivery time corresponds to the duration from the moment when the R wave is detected to the moment when the delivery of a cardiac stimulation pulse is triggered; and the cardiac stimulation pulse generator (2) is used for delivering the cardiac stimulation pulse to the control electrode (3) according to the pulse delivery time. In this way, multi-part electrical stimulation of the left ventricle and the right ventricle is realized.

Abstract: A method for controlling a landing gear of an aerial vehicle includes determining whether a relative height of the aerial vehicle is greater than a height threshold and, in response to the relative height being not greater than the height threshold and the aerial vehicle having not lowered the landing gear, adjusting the relative height to the height threshold or above, and lowering the landing gear. The relative height is a vertical height of the aerial vehicle with respect to an object, and the height threshold is a safe flight height.

Abstract: Disclosed is a pixel circuit including a drive sub-circuit, a writing sub-circuit, a first reset sub-circuit, and a light emitting element. The drive sub-circuit is configured to provide a drive current between a first electrode and a second electrode of the drive sub-circuit in response to a control signal of a first node; the writing sub-circuit is configured to write a data voltage signal to the first electrode of the drive sub-circuit in response to a control signal of a first scan signal line; the first reset sub-circuit is configured to reset an anode terminal of the light emitting element in response to a control signal of a second scan signal line; and in a low frequency display mode, an input frequency of the control signal of the first scan signal line is the same as a data refresh frequency.

Abstract: A pixel circuit includes a data writing sub-circuit, a reset sub-circuit and a leakage prevention sub-circuit. The data writing sub-circuit is configured to: in a data writing period, store a light-emitting compensation signal in response to a gate scan signal from a first scan signal terminal and a data signal from a data signal terminal; and in a light-emitting period, assist in controlling the light-emitting control sub-circuit to be turned on according to the light-emitting compensation signal. The reset sub-circuit is configured to: in a reset period, transmit an initial voltage signal to the data writing sub-circuit and the leakage prevention sub-circuit in response to a reset scan signal from a second scan signal terminal. The leakage prevention sub-circuit is configured to: in the data writing period, store another light-emitting compensation signal; and in the light-emitting period, inhibit leakage of the reset sub-circuit according to the another light-emitting compensation signal.

Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a storage capacitor (Cst) having a first capacitor electrode (Ce1) and a second capacitor electrode (Ce2); a driving transistor (Td) configured to generate a driving current; and a switch (SW) configured to control connection or disconnection between a gate electrode of the driving transistor (Td) and the first capacitor electrode (Ce1).

Abstract: An array substrate and a display device are provided. The array substrate includes a plurality of pixel driving circuits, each of which includes a driving transistor, a first light emitting control transistor, a compensation transistor, a first initialization transistor and a second initialization transistor; a first electrode of the first initialization transistor and a first electrode of the first light emitting control transistor are connected to a first node; a first electrode of the second initialization transistor and a first electrode of the compensation transistor are connected to a second node, a second electrode of the first initialization transistor is configured to receive the first initialization signal, and a cathode of the light emitting element is configured to receive a first driving signal, and a difference between a potential of the first initialization signal and a potential of the first driving signal is less than 1.5V.

Abstract: Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a plurality of sub-pixels, each sub-pixel including a light-emitting element and a pixel driving circuit; a plurality of gate lines and light-emitting control lines; a gate driving circuit located at the display area and including cascaded multistage gate driving units, one or more stages include gate driving sub-circuits including a first and a second gate driving sub-circuit spaced apart by pixel driving circuits of a first group of sub-pixels; and a light-emitting control driving circuit located at the display area and including cascaded multistage light-emitting control driving units, one or more stages include light-emitting control driving sub-circuits including a first and a second light-emitting control driving sub-circuit spaced apart by pixel driving circuits of a second group of sub-pixels.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a pixel unit, including a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor and a threshold compensation transistor; a first power line configured to supply a first power supply voltage to the pixel circuit; a blocker, electrically connected with the first power line; and a first conductive structure, connected with the gate electrode of the driving transistor, the first channel and the second channel of the threshold compensation transistor are connected by a conductive connection portion; an area of an orthographic projection of a portion of the blocker overlapping with the first conductive structure on the base substrate is larger than an area of an orthographic projection of a portion of the blocker overlapping with the conductive connection portion on the base substrate.

Abstract: A display substrate and a display panel. The display substrate includes: a base substrate; and a plurality of sub-pixels on the base substrate, each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a current-leakage prevention sub-circuit and a storage sub-circuit; the storage sub-circuit includes a storage capacitor, the storage capacitor includes a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate and the third electrode plate are electrically connected to each other and are in different layers with respect to the base substrate, and the second electrode plate at least partially overlaps the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate.

Abstract: The embodiments of the present disclosure provides a display substrate, including: an active region and a peripheral region, the active region is provided therein with a plurality of pixel units arranged in an array, all the pixel units are divided into n pixel unit groups, the peripheral region is provided therein with a driver block including a first gate drive circuit having n+x first signal output terminals configured to sequentially output first gate drive signals in an active level and the first gate line provided for an ith pixel unit group is electrically connected to a (i+x)th first signal output terminal, and the reset signal line provided for the ith pixel unit group is electrically connected to an ith first signal output terminal, with i being a positive integer and i?n.

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first control circuit, a compensation control circuit and a first initialization circuit; the first control circuit is configured to control to connect the control end of the driving circuit and the connection node under the control of a first scan signal; the compensation control circuit is configured to control to connect the connection node and the first end of the driving circuit under the control of a second scan signal; the first initialization circuit is configured to write a first initialization voltage into the connection node under the control of an initialization control signal; the driving circuit is configured to control to connect the first end and a second end of the driving circuit under the control of a potential of the control end thereof.

Abstract: A substrate with a crack detection function, comprising an installation area for installing hardware, a wiring area, and a detection assembly. The wiring area is set around the installation area. The detection assembly is in the wiring area. The detection assembly includes a plurality of detecting units and a plurality of connecting units. The plurality of detecting units is set around the wiring area. Two ends of each connecting unit are respectively connected to two detecting units, forming a circuit for detecting whether cracks exist in the substrate. Each detecting unit includes at least two detecting endpoints. Each connecting unit includes at least two detecting wires, with each end of one detecting wire connected to one detecting endpoint of two detecting units. The at least two detecting wires between two non-adjacent detecting units are set around outside of the installation area to form a closed loop area.

Abstract: A method for generating a radiation treatment plan is provided. The method may include determining a set of one or more optimization goals for radiation delivery by a therapeutic radiation delivery apparatus. The method may also include determining a plan for radiation delivery from a radiation source of the therapeutic radiation delivery apparatus. The radiation source may be capable of continuously rotating around a subject. The plan may include a plurality of radiation segments. Each radiation segment may be characterized by at least one parameter selected from a start angle, a stop angle, a two-dimensional segment shape, or a segment MU value such that the plurality of radiation segments satisfy the set of one or more optimization goals by superimposing at least two radiation segments from at least two different rotations into a target volume of the subject.

Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.