Patents by Inventor Li-Wei Liu

Li-Wei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508585
    Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Patent number: 11508614
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 22, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Patent number: 11482450
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
  • Patent number: 11476288
    Abstract: A method includes epitaxially growing a first III-V compound layer over a semiconductive substrate. A second III-V compound layer is epitaxially grown over the first III-V compound layer. A source/drain contact is formed over the second III-V compound layer. A gate structure is formed over the second III-V compound layer. A pattern is formed shielding the gate structure and the source/drain contact, in which a portion of the second III-V compound layer is free from coverage by the pattern.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ying Wu, Li-Hsin Chu, Chung-Chuan Tseng, Chia-Wei Liu
  • Patent number: 11464450
    Abstract: A fixed-sensor finger action detecting glove has a glove body, five covering sheets, five fixing bases, five sensors, and five fixing assemblies. A side of the glove body forms a hand back section and five finger back sections. The covering sheet is mounted on the finger back section and forms a passage. The fixing base is made from a flexible material, is mounted through the passage, and has two limiting walls. The sensor is located in the passage between the two limiting walls, preventing the sensor from deviating. The fixing assembly is mounted between an end of the sensor and an end of the finger back section, detachably connects the sensor and the finger back section, and prevents the sensor from moving back and forth. Thus, the fixed-sensor finger action detecting glove is capable of detecting actions of the fingers precisely.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 11, 2022
    Assignee: REHABOTICS MEDICAL TECHNOLOGY CORP.
    Inventors: Jian-Jia Huang, Shu-Wei Pu, Tsung-Fu Liu, Pin-Tseng Liu, Li-Wei Cheng
  • Publication number: 20220308727
    Abstract: The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes a substrate, a copper layer, an organic composite protective layer, and a silver nanowire layer. The copper layer is disposed on the substrate. The nanowire-distribution-promotion layer is disposed between the copper layer and the silver nanowire layer.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: Xi-Zhao Wang, Yi-Min Jiang, Li-Wei Mu, Shan-Yu Wu, Chao-Hui Kuo, Can-Liang Zhao, Hong-Yan Lian, Chun-Wei Liu
  • Publication number: 20220305717
    Abstract: The present invention relates to a process of fabricating a multi-layer composite structure by 3D printing, said composite structure comprises at least one cured mortar layer formed by curing of a mortar composition, and at least one polyurethane layer formed by polymerization of a first polyurethane forming composition, wherein said mortar composition and said first polyurethane forming composition are dispensed individually and simultaneously via adjacent printing nozzles. The mortar composition is optionally modified by a second polyurethane forming composition.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 29, 2022
    Inventors: Hang XU, ShengZhong ZHOU, Bang Wei XI, Xi Tao LIU, Li Xia WANG, He Meng ZHAO, Bernhard FEICHTENSCHLAGER, Stefan HIRSEMANN
  • Patent number: 11455931
    Abstract: A source driving circuit of a display includes a gamma resistor strings, a digital to analog (DAC) circuit, and an output buffer circuit. The output buffer circuit includes input stage module, gain stage module, and output stage module. The input stage module includes main input stage unit and auxiliary input stage unit. Sizes of elements in main input stage unit are larger than sizes of elements in the auxiliary input stage unit, smaller sizes presenting smaller parasitic capacitances. During the switching period, the auxiliary input stage unit, gain stage module, and output stage module form a first unity gain amplifier outputting the driving voltages. During the stable period, the main input stage unit, gain stage module, and output stage module form a second unity gain amplifier outputting the driving voltages. A display device is also disclosed.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 27, 2022
    Assignee: Fitipower Integrated Technology, Inc.
    Inventors: Li-Wei Liu, Bo-Wen Huang, Chun-Yung Cho
  • Publication number: 20220223996
    Abstract: An electronic device including a first body, a second body, and at least one cavity antenna module is provided. The second body has a pivot side and a plurality of non-pivot sides, and the pivot side is connected pivotally to the first body. The cavity antenna module includes a metal cavity body and a first antenna structure. The metal cavity body is disposed in the second body and has an opening. A distance between one of the non-pivot sides and the metal cavity body is smaller than a distance between the pivot side and the metal cavity body, and the opening faces the one of the non-pivot sides. The first antenna structure is disposed in the opening of the metal cavity body, and the first antenna structure includes a feeding portion, a radiating portion, and a ground portion connected with one another.
    Type: Application
    Filed: October 21, 2021
    Publication date: July 14, 2022
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Jhih-Ciang Chen, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Chih-Heng Lin, Je-Wei Liao, Chun-Cheng Chan, Jui-Hung Lai
  • Patent number: 11387148
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: July 12, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Patent number: 11069690
    Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 20, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Shih-Kuei Yen, Li-Wei Liu, Le-Tien Jung, Hung-Lin Shih, Hsuan-Tung Chu, Ming-Che Li, Guan-Yi Liou, Huai-Jin Hsing
  • Patent number: 10763402
    Abstract: A light-emitting diode package includes a substrate, at least one light-emitting chip, a light-reflective layer and a wave-length conversion fluorescent layer. The light-emitting chip is located on the substrate. The light-reflective layer is arranged around the light-emitting chip. The wave-length conversion fluorescent layer is located over the light-emitting chip, wherein the light-reflective layer is spaced from the fluorescent wave-length conversion layer by a groove that reaches two opposite sides of the light-emitting diode package.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 1, 2020
    Assignee: Lextar Electronics Corporation
    Inventors: Shang-Hsun Tsai, Li-Wei Liu
  • Publication number: 20200083228
    Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
    Type: Application
    Filed: September 28, 2018
    Publication date: March 12, 2020
    Inventors: Shih-Kuei Yen, Li-Wei Liu, Le-Tien Jung, Hung-Lin Shih, Hsuan-Tung Chu, Ming-Che Li, Guan-Yi Liou, Huai-Jin Hsing
  • Publication number: 20190245121
    Abstract: A light-emitting diode package includes a substrate, at least one light-emitting chip, a light-reflective layer and a wave-length conversion fluorescent layer. The light-emitting chip is located on the substrate. The light-reflective layer is arranged around the light-emitting chip. The wave-length conversion fluorescent layer is located over the light-emitting chip, wherein the light-reflective layer is spaced from the fluorescent wave-length conversion layer by a groove that reaches two opposite sides of the light-emitting diode package.
    Type: Application
    Filed: December 5, 2018
    Publication date: August 8, 2019
    Inventors: Shang-Hsun TSAI, Li-Wei LIU
  • Patent number: 10361209
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 23, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Patent number: 10154620
    Abstract: A manufacturing method of a casing is provided. First, a plate, a frame and a main shell are provided, wherein the plate has an adhering region and at least one thermal fusion region, and the frame has a first surface and a second surface opposite to each other. Then, the plate is stacked on the first surface of the frame, wherein the thermal fusion region is overlapped with the frame, and the adhering region is not overlapped with the frame. The main shell is adhered to the adhering region of the plate and the second surface of the frame. The thermal fusion region is fixed to the frame by thermal fusion. In addition, a casing manufactured through the above-mentioned method is also provided.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: December 11, 2018
    Assignee: Wistron Corporation
    Inventors: Li-Wei Liu, Liang Yu
  • Publication number: 20180350817
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Publication number: 20180261603
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Application
    Filed: April 5, 2017
    Publication date: September 13, 2018
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Patent number: 10074656
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: September 11, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Patent number: 10056035
    Abstract: A pixel circuit includes a first capacitor, an input unit, a driving unit, a first compensation unit, an organic light-emitting diode, a switch unit, a second compensation unit and a reset unit. The input unit is electrically connected to the first capacitor and the second compensation unit. The second compensation unit is electrically connected to the organic light-emitting diode. The first compensation unit is electrically connected to the first capacitor, the driving unit, the switch unit and the reset unit. The driving unit is electrically connected to the switch unit and the reset unit. The switch unit is electrically connected to the organic light-emitting diode. The pixel circuit is configured to generate a corresponding driving current according to a turn-on voltage of the organic light-emitting diode. A driving method of a pixel circuit is also provided.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 21, 2018
    Assignee: AU OPTRONICS CORP.
    Inventors: Li-Wei Liu, Chien-Ya Lee