Patents by Inventor Li-Wei Liu

Li-Wei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210371702
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: December 2, 2021
    Inventors: JI CUI, CHI-JEN LIU, LIANG-GUANG CHEN, KEI-WEI CHEN, CHUN-WEI HSU, LI-CHIEH WU, PENG-CHUNG JANGJIAN, KAO-FENG LIAO, FU-MING HUANG, WEI-WEI LIANG, TANG-KUEI CHANG, HUI-CHI HUANG
  • Publication number: 20210366372
    Abstract: A sub-pixel array and a display are provided. The sub-pixel structure includes a driving module, a first selection module, a second selection module, a switch module, a first light-emitting element, and a second light-emitting element. The first selection module is configured to control conduction between the driving module and an anode of the first light-emitting element or conduction between the driving module and an anode of the second light-emitting element through a first control signal. The second selection module is configured to control grounding of a cathode of the first light-emitting element or grounding of a cathode of the second light-emitting element through a second control signal.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 25, 2021
    Inventors: Jia SUN, Ying-chi WANG, Chia-huang YEN, Li-wei KUNG, Cheng-ming LIU
  • Publication number: 20210335648
    Abstract: A device, apparatus, and method for semiconductor transfer are provided. A transfer substrate is controlled to be moved to be above the target substrate. An infrared emitting portion emits infrared signals to position a semiconductor on a target substrate. After a second magnetic portion picks up the semiconductor from the target substrate, a controller outputs a first control current to a first electromagnetic portion to cause the first electromagnetic portion to generate an electromagnetic force, to control the second magnetic portion to adjust a position of the picked-up semiconductor relative to the welding position on the target substrate, where adjusting the position of the picked up semiconductor includes horizontal adjustment.
    Type: Application
    Filed: July 7, 2021
    Publication date: October 28, 2021
    Inventors: Qiyuan WEI, Ying-chi WANG, Cheng-ming LIU, Chien-hung LIN, Li-wei KUNG
  • Publication number: 20210312965
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
  • Patent number: 11127625
    Abstract: A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a first semiconductor substrate. In various embodiments, at least a portion of the device layer is separated from the first semiconductor substrate, where the separating forms a cleaved surface on the separated portion of the device layer. In some examples, a patterned low-K dielectric layer is formed on a second semiconductor substrate. Thereafter, and in some embodiments, the separated portion of the device layer is bonded, along the cleaved surface, to the patterned low-K dielectric layer.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsiang Tsai, Chung-Chuan Tseng, Li Hsin Chu, Chia-Wei Liu
  • Patent number: 11101209
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Patent number: 11069690
    Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 20, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Shih-Kuei Yen, Li-Wei Liu, Le-Tien Jung, Hung-Lin Shih, Hsuan-Tung Chu, Ming-Che Li, Guan-Yi Liou, Huai-Jin Hsing
  • Patent number: 10763402
    Abstract: A light-emitting diode package includes a substrate, at least one light-emitting chip, a light-reflective layer and a wave-length conversion fluorescent layer. The light-emitting chip is located on the substrate. The light-reflective layer is arranged around the light-emitting chip. The wave-length conversion fluorescent layer is located over the light-emitting chip, wherein the light-reflective layer is spaced from the fluorescent wave-length conversion layer by a groove that reaches two opposite sides of the light-emitting diode package.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 1, 2020
    Assignee: Lextar Electronics Corporation
    Inventors: Shang-Hsun Tsai, Li-Wei Liu
  • Publication number: 20200083228
    Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.
    Type: Application
    Filed: September 28, 2018
    Publication date: March 12, 2020
    Inventors: Shih-Kuei Yen, Li-Wei Liu, Le-Tien Jung, Hung-Lin Shih, Hsuan-Tung Chu, Ming-Che Li, Guan-Yi Liou, Huai-Jin Hsing
  • Publication number: 20190245121
    Abstract: A light-emitting diode package includes a substrate, at least one light-emitting chip, a light-reflective layer and a wave-length conversion fluorescent layer. The light-emitting chip is located on the substrate. The light-reflective layer is arranged around the light-emitting chip. The wave-length conversion fluorescent layer is located over the light-emitting chip, wherein the light-reflective layer is spaced from the fluorescent wave-length conversion layer by a groove that reaches two opposite sides of the light-emitting diode package.
    Type: Application
    Filed: December 5, 2018
    Publication date: August 8, 2019
    Inventors: Shang-Hsun TSAI, Li-Wei LIU
  • Patent number: 10361209
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 23, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Patent number: 10154620
    Abstract: A manufacturing method of a casing is provided. First, a plate, a frame and a main shell are provided, wherein the plate has an adhering region and at least one thermal fusion region, and the frame has a first surface and a second surface opposite to each other. Then, the plate is stacked on the first surface of the frame, wherein the thermal fusion region is overlapped with the frame, and the adhering region is not overlapped with the frame. The main shell is adhered to the adhering region of the plate and the second surface of the frame. The thermal fusion region is fixed to the frame by thermal fusion. In addition, a casing manufactured through the above-mentioned method is also provided.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: December 11, 2018
    Assignee: Wistron Corporation
    Inventors: Li-Wei Liu, Liang Yu
  • Publication number: 20180350817
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Publication number: 20180261603
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Application
    Filed: April 5, 2017
    Publication date: September 13, 2018
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Patent number: 10074656
    Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: September 11, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
  • Patent number: 10056035
    Abstract: A pixel circuit includes a first capacitor, an input unit, a driving unit, a first compensation unit, an organic light-emitting diode, a switch unit, a second compensation unit and a reset unit. The input unit is electrically connected to the first capacitor and the second compensation unit. The second compensation unit is electrically connected to the organic light-emitting diode. The first compensation unit is electrically connected to the first capacitor, the driving unit, the switch unit and the reset unit. The driving unit is electrically connected to the switch unit and the reset unit. The switch unit is electrically connected to the organic light-emitting diode. The pixel circuit is configured to generate a corresponding driving current according to a turn-on voltage of the organic light-emitting diode. A driving method of a pixel circuit is also provided.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 21, 2018
    Assignee: AU OPTRONICS CORP.
    Inventors: Li-Wei Liu, Chien-Ya Lee
  • Publication number: 20180190661
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; performing an ion implantation process to implant ions into the substrate underneath the trench; performing an in-situ steam generation (ISSG) process to form a gate dielectric layer in the trench; forming a gate electrode on the gate dielectric layer; and forming a doped region in the substrate adjacent to two sides of the gate electrode.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 5, 2018
    Inventors: Yung-Ming Wang, Li-Wei Liu, Shu-Yen Chan, Yukihiro Nagai, Tien-Chen Chan, Ger-Pin Lin
  • Patent number: 9812061
    Abstract: A display apparatus includes a display unit, a source driver, a gate driver and a compensation unit. The display unit includes at least a pixel unit. Each pixel unit includes a first transistor, a second transistor, a first capacitor, a second capacitor and an organic light emitting diode. When the pixel unit is operated in a display mode, the pixel unit outputs a sensing voltage including a first parameter having characteristics of the second transistor and a second parameter having characteristics of the organic light emitting diode. The source driver receives a compensation data and accordingly adjusts the next display data. The compensation unit is disposed between the second capacitor and the source driver and electrically coupled between the second end of the second capacitor and the source driver. The compensation unit receives the sensing voltage and outputs the compensation data according to the received sensing voltage.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: November 7, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Li-Wei Liu, Yi-Cheng Lin
  • Publication number: 20170162118
    Abstract: A pixel circuit includes a first capacitor, an input unit, a driving unit, a first compensation unit, an organic light-emitting diode, a switch unit, a second compensation unit and a reset unit. The input unit is electrically connected to the first capacitor and the second compensation unit. The second compensation unit is electrically connected to the organic light-emitting diode. The first compensation unit is electrically connected to the first capacitor, the driving unit, the switch unit and the reset unit. The driving unit is electrically connected to the switch unit and the reset unit. The switch unit is electrically connected to the organic light-emitting diode. The pixel circuit is configured to generate a corresponding driving current according to a turn-on voltage of the organic light-emitting diode. A driving method of a pixel circuit is also provided.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 8, 2017
    Inventors: LI-WEI LIU, CHIEN-YA LEE
  • Publication number: 20170159196
    Abstract: An electrical deposition apparatus includes a brush plating head. The brush plating head includes a plurality of channels, and there are openings at the same surface of the brush plating head. Each of the channels extends from within the brush plating head to each of the openings.
    Type: Application
    Filed: August 30, 2016
    Publication date: June 8, 2017
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Fu Lu, Ya-Ching Chou, Li-Wei Liu, Hsin-Hwa Chen