Patents by Inventor Li-Wen Weng

Li-Wen Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor having notched fin structure and method of making the same
    Patent number: 8759943
    Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Tseng, Da-Wen Lin, Chien-Tai Chan, Chia-Pin Lin, Li-Wen Weng, An-Shen Chang, Chung-Cheng Wu
  • Multiple-gate semiconductor device and method
    Patent number: 8426923
    Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: April 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Da-Wen Lin, Hsien-Chin Lin
  • TRANSISTOR HAVING NOTCHED FIN STRUCTURE AND METHOD OF MAKING THE SAME
    Publication number: 20120086053
    Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).
    Type: Application
    Filed: October 8, 2010
    Publication date: April 12, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hung TSENG, Da-Wen LIN, Chien-Tai CHAN, Chia-Pin LIN, Li-Wen WENG, An-Shen CHANG, Chung-Cheng WU
  • Multiple-Gate Semiconductor Device and Method
    Publication number: 20110127610
    Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.
    Type: Application
    Filed: June 9, 2010
    Publication date: June 2, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Da-Wen Lin, Hsien-Chin Lin