Patents by Inventor Li-Ya LAI

Li-Ya LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device
    Patent number: 10770142
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 8, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wen-Zhang Lin, Li-Ya Lai
  • Control circuit configured to terminate a set operation and a reset operation of a resistive memory cell of memory array based on the voltage variation on the data line of the resistive memory cell
    Patent number: 10607698
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 31, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wen-Zhang Lin, Li-Ya Lai
  • MEMORY DEVICE
    Publication number: 20190115074
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Meng-Fan CHANG, Wen-Zhang LIN, Li-Ya LAI
  • CONTROL CIRCUIT OF A RESISTIVE MEMORY CELL OF A MEMORY ARRAY
    Publication number: 20190115075
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Meng-Fan CHANG, Wen-Zhang LIN, Li-Ya LAI
  • Control circuit configured to terminate a set operation and a reset operation of a resistive memory cell of memory array based on the voltage variation on the data line of the resistive memory cell
    Patent number: 10204681
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: February 12, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wen-Zhang Lin, Li-Ya Lai
  • WRITE TERMINATION WITH AUTO-WRITE FOR RESISTIVE TYPE MEMORY
    Publication number: 20180330785
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 15, 2018
    Inventors: Meng-Fan CHANG, Wen-Zhang LIN, Li-Ya LAI