Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.