Abstract: A method for fabricating a micro-electro-mechanical system (MEMS) device includes following steps. A cap layer is formed on an MEMS structure. The MEMS structure has a plurality of sacrificial structures. The cap layer has a plurality of release holes. The release holes are located on the sacrificial structures. A dielectric layer is formed on the cap layer, and the dielectric layer fills the release holes. A planarization process is performed on the dielectric layer. The sacrificial structures are then removed to form at least one cavity in the MEMS structure.

Abstract: A method of fabricating a non-volatile memory device is provided. A substrate including a first region and a second region is provided. Then, an uneven surface is formed on the substrate in the second region. Thereafter, a doped layer is formed in the substrate in the second region, and the doped layer is served as a control gate. Afterward, a dielectric layer is formed on the substrate in the first region and on the uneven surface of the substrate in the second region. Next, a floating gate is formed on the dielectric layer, and the floating gate is extended from the first region to the second region. Source and drain regions are formed in the substrate at opposite sides of the floating gate in the first region.

Abstract: A non-volatile memory device including a substrate, a dielectric layer, a floating gate, source and drain regions, a channel region, and a doped layer is provided. The substrate includes a first region and a second region, and the substrate has an uneven surface in the second region. The dielectric layer is located on the substrate in the first region and in the second region to cover the uneven surface. The floating gate is located on the dielectric layer in the first region and is continuously extended to the second region. The source and drain regions are located in the substrate at opposite sides of the floating gate in the first region. The channel region is located in the substrate between the source and drain regions. The doped layer is located on the uneven surface or in the substrate in the second region to serve as a control gate.

Abstract: This invention provides a method of forming a self-aligned silicide of a semiconductor wafer, the surface of the semiconductor wafer comprising at least one silicon device. A cobalt-containing metallic layer is formed on the semiconductor wafer which covers on the surface of the silicon device. A first thermal treatment process is performed to rapidly heat the semiconductor wafer up to 300˜500° C. for 10˜50 seconds and form Co2Si on the surface of the silicon device. A second thermal treatment process is performed to rapidly heat the semiconductor wafer up to 400˜680° C. for 20˜50 seconds and then cool down the semiconductor wafer afterwards so as to convert Co2Si into CoSi. An etching process is performed to remove the metallic layer. A third thermal treatment process is performed to rapidly heat the semiconductor wafer up to 700˜950° C. for 30˜60 seconds and then cool down the semiconductor wafer afterward so as to convert CoSi into the self-aligned silicide.

Abstract: Several processes for forming semiconductor gate structures having treated titanium silicide layers are disclosed. There are at least three methods been provided for the present invention and a summarized general procedure of all the methods comprises the following steps: The first step is to provide a silicon substrate having a gate oxide layer formed on top the silicon substrate, and forming a polysilicon layer over the gate oxide layer, followed by the formation of a TiN layer over the polysilicon layer. A treated titanium silicide layer is then formed on top of the TiN layer. Sequentially, an anti-reflection (SiON) film is deposited on top of the treated titanium silicide layer with a capping layer formed over the anti-reflection film. Finally, patterning and etching the above layers to expose a portion of the gate oxide layer and to form a gate electrode, where the final gate structure is rounded up by a rapid thermal process (RTP).

Abstract: A thin silicon dioxide layer is formed on the substrate to act as a pad layer. Subsequently, a silicon nitride layer is deposited on the pad layer. Trenches are formed in the substrate. The trenches include first trenches and a second trench that has a relatively wide opening compared to the first trenches. An CVD-oxide layer is formed on the silicon nitride layer and refilled into the trenches. A multi-layer is then formed on the CVD-oxide layer. The multi-layer includes alternating PE-nitride layers and PE-oxide layers. Subsequently, a chemical mechanical polishing (CMP) technology is used for removing the multi-layer layer to the surface of the silicon nitride layer.

Abstract: An array of DRAM cells having brush-shaped stacked capacitors with increased capacitance is achieved. A first planar insulating layer is formed having openings over the FET source/drain areas for node contacts. A doped first polysilicon layer and a silicide layer are deposited and patterned to form bit lines and concurrently form the capacitor node contacts in the openings. A planar second insulating layer is deposited with second openings aligned over the node contacts. A multilayer composed of a doped second polysilicon layer, an etch end-stop layer (silicide or undoped polysilicon), a thick doped third polysilicon layer, and a thin insulating layer is deposited and patterned to form the capacitor bottom electrodes. A thin hemispherical-shaped grain (HSG) fourth polysilicon layer is deposited and used as an etch mask to form a sieve-like mask in the third insulating layer on the top of the bottom electrode.

Abstract: DRAM cells having zigzag-shaped stacked capacitors with hemispherical gain (HSG) surfaces to increase capacitance is achieved. FET gate electrodes are formed having a planar first insulating layer thereon. Contact openings are etched for bit line contacts and capacitor node contacts. A first polysilicon layer having a top silicide layer is patterned to form bit lines and node contacts. A planar second insulating layer is formed with openings to the node contacts, which are filled with a second polysilicon to form electrical connections. A etch-stop layer is deposited followed by a multilayer composed of alternating layers of phosphosilicate and borosilicate glass. Recesses are etched in the multilayer to the node contacts, and the sidewalls in the recesses are isotropically etched to form a zigzag profile. A doped amorphous silicon layer is deposited and treated to form a HSG layer. An insulating layer is formed in the recesses to provide an etch mask and the HSG layer is etched back.

Abstract: A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is deposited and etched back to form sidewall-spacer bit lines. A planar second insulating layer is formed in which bit line contact openings are etched between the sidewall-spacer bit lines to the first source/drain areas. The contact openings are filled with a third conducting layer to form the bit line contacts. A third insulating layer is deposited and capacitor node contact openings are etched between the sidewall-spacer bit lines and to the second source/drain areas. An insulating layer is deposited and etched back to insulate the sidewall-spacer bit lines in the node contact openings and a fourth con-ducting layer is deposited and etched back to form the node contacts.

Abstract: A crown capacitor for a memory device is formed using (1) an important early poly plug 42 process and (2) an etch barrier layer 34. A first insulating layer 30 and an etch barrier layer are formed over device structures and the substrate 10. A node contact hole 40 is formed through the etch barrier layer 34 and the first insulating layer 30. A plug 42 is formed filling the node contact hole 40. Next, a planarizing layer 44 is formed over the etch barrier layer 34 and the plug 42. A crown hole 46 is formed in the planarizing layer 44 exposing the plug 42. A first polysilicon layer 50 is deposited over the etch barrier layer, the plug 42, and the remaining first planarizing layer 44A. A Sacrificial layer 54 is formed over the first polysilicon layer 50 thereby filling the crown hole 46. The sacrificial layer 54 and the first polysilicon layer 50 are etch back to remove the exposed portions of the first polysilicon layer 50 over the planarizing layer 44A.

Abstract: A method of forming a capacitor having a cross section shape similar to the Greek letter psi. The shape of the capacitor plate provides a high capacitance using a modest amount of chip area. A capacitor hole is etched in a thick layer of a first dielectric. A layer of polysilicon is formed on the dielectric layer covering the sidewalls and bottom of the capacitor hole. A second dielectric is then used to fill the hole. A contact hole in the second dielectric extends to the contact region of the wafer and is filled with a polysilicon plug. The polysilicon plug and the polysilicon covering the sidewalls and bottom of the capacitor hole form the first capacitor plate. A layer of hemispherical grain polysilicon can be used to further increase the surface area of the first capacitor plate.

Abstract: A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is deposited and etched back to form sidewall-spacer bit lines. A planar second insulating layer is formed in which bit line contact openings are etched between the sidewall-spacer bit lines to the first source/drain areas. The contact openings are filled with a third conducting layer to form the bit line contacts. A third insulating layer is deposited and capacitor node contact openings are etched between the sidewall-spacer bit lines and to the second source/drain areas. An insulating layer is deposited and etched back to insulate the sidewall-spacer bit lines in the node contact openings and a fourth con-ducting layer is deposited and etched back to form the node contacts.

Abstract: A polysilicon layer is deposited on a dielectric layer. A silicon oxynitride layer is then formed on the polysilicon layer. A photoresist is imprinted with a pattern on the silicon oxynitride layer to define the storage node. An etching step is used to etch the silicon oxynitride layer and the polysilicon layer to formed the storage node. A HSG silicon is deposited on the silicon oxynitride layer and on the side walls of the storage node. An isotropically etching step is performed to remove the HSG layer on the top of the storage node. The silicon oxynitride is then removed. A dielectric layer is then formed along the surface of the storage node. A conductive layer is deposited over the dielectric layer. The conductive layer is used as the top storage node.