Patents by Inventor Li Yi-Lin

Li Yi-Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11416665
    Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 16, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Chen Huang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao, Chih-Chan Chen, Chia-Jung Hsu, Li-Yi Lin
  • Patent number: 11030379
    Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: June 8, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tien-Kuo Lin, Li-Yi Lin, Yun-Chih Chang
  • Patent number: 10997353
    Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 4, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: I-Ching Tsai, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Publication number: 20210124864
    Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 29, 2021
    Inventors: Cheng-Chen HUANG, Yun-Ru WU, Hsin-Chang LIN, Shu-Yi KAO, Chih-Chan CHEN, Chia-Jung HSU, Li-Yi LIN
  • Patent number: 10936784
    Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Publication number: 20210034808
    Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 4, 2021
    Inventors: TIEN-KUO LIN, LI-YI LIN, YUN-CHIH CHANG
  • Publication number: 20210004516
    Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.
    Type: Application
    Filed: May 28, 2020
    Publication date: January 7, 2021
    Inventors: I-Ching TSAI, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Publication number: 20210004520
    Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.
    Type: Application
    Filed: December 5, 2019
    Publication date: January 7, 2021
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Publication number: 20090064067
    Abstract: A method of balancing the path delay of a clock tree for minimizing clock skew of the clock tree in the IC layouts is described.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Applicant: Silicon Integrated Systems Corp.
    Inventors: Tsung-hsin Liu, Li-yi Lin
  • Patent number: 7199265
    Abstract: This invention relates to compounds of the formula (I) which are thyroid receptor ligands, and are preferably selective for the thyroid hormone receptor ?, to methods of preparing such compounds and to methods for using such compounds such as in the regulation of metabolism.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: April 3, 2007
    Assignee: Karo Bio AB
    Inventors: Li Yi-Lin, Johan Malm, Chris Litten, Ana Maria Garcia Collazo, Neeraj Garg
  • Publication number: 20040097589
    Abstract: This invention relates to compounds of the formula (I) which are thyroid receptor ligands, and are preferably selective for the thyroid hormone receptor &bgr;, to methods of preparing such compounds and to methods for using such compounds such as in the regulation of metabolism.
    Type: Application
    Filed: April 22, 2003
    Publication date: May 20, 2004
    Inventors: Li Yi-Lin, Johan Malm, Chris Litten, Ana Maria Garcia Collazo, Neeraj Garg