Abstract: The present disclosure describes semiconductor devices and methods for forming the same. A method for forming a semiconductor device includes forming a source/drain structure and forming a gate structure. The method also includes performing a cleaning process on the source/drain structure and the gate structure. The method also includes disposing a portion of a byproduct of the cleaning process on a top surface of the gate structure and etching the portion of the byproduct so a remaining portion of the byproduct is formed on the top surface of the gate structure. The method further includes forming a gate contact structure, including depositing a metal material on the remaining portion of the byproduct to form a compound containing the metal material and the remaining portion of the byproduct. The method also includes forming a barrier layer between the compound and the top surface of the gate structure.

Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.

Abstract: Embodiments of the present disclosure provide a FinFET transistor having a gate structure including one or more non-conformal work function metal layers. In some embodiments, work function metal layers may be non-conformal in at least one of thickness, composition, and/or phases. The non-conformality in the work function metal layer lowers leakage, improve device performance, and increase device reliability.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment includes forming a plurality of fins protruding from a substrate, forming first and second dummy gate stacks over the fins, and depositing a cover structure over the fins. A first portion of the cover structure extends between the first and second dummy gate stacks. The method also includes etching the fins to form a first trench between the first dummy gate stack and the first portion of the cover structure and a second trench between the second dummy gate stack and the first portion of the cover structure, removing the cover structure, epitaxially growing a first epitaxial feature from the first trench and a second epitaxial feature from the second trench. The first and second epitaxial features merge after rising above a top surface of the fins.

Abstract: A semiconductor structure a method of fabricating thereof including a substrate having a device region and a dummy region. A first active region is disposed over the substrate in the device region and a second active region is over the substrate in the dummy region. A first operational gate structure over the first active region and a first non-operational gate structure over the second active region. A first epitaxial region of an n-type dopant is adjacent the first operation gate structure; and a second epitaxial region of an n-type dopant is adjacent the first non-operational gate structure.

Abstract: Embodiments of the present disclosure provide a FinFET semiconductor including a first set of fin structures that are active, a source/drain (S/D) region in contact with the first set of fin structures, a second set of fin structures separated, via a shallow trench isolation (STI) feature, from the first set of fin structures, a contact etch stop layer (CESL) over the S/D region and over the second set of fin structures, and a gate over the first set of fin structures and over the second set of fin structures, the gate including a gate dielectric and a gate electrode over the gate dielectric. The second set of fin structures includes one or more non-active fin structures that are in contact with the CESL without being in contact with the S/D region.

Abstract: A positioning system based on a sector depth camera is disclosed. The positioning system comprises: a sector depth camera used for acquiring 3D point cloud data within a sector range of a preset angle in a horizontal direction and transmitting the 3D point cloud data to a positioning optimization module; an image acquisition device used for acquiring image data and transmitting the image data to the positioning optimization module; an inertial sensor used for acquiring IMU data and transmitting the IMU data to the positioning optimization module; and the positioning optimization module used for receiving the 3D point cloud data transmitted by the sector depth camera, the image data transmitted by the image acquisition device, and the IMU data transmitted by the inertial sensor, and optimizing the 3D point cloud data based upon the image data and the IMU data to obtain an optimized location information.

Abstract: A method for correcting a determination threshold of a floor medium and a method of detecting thereof are provided. The method is used for controlling a mobile robot equipped with a sound emitter and a sound receiver to detect and recognize the floor medium during a movement just started. A first detection result of a current floor medium is obtained by actively transmitting and receiving a sound signal, then, a to-be-adjusted detection result of the current floor medium is obtained only by passively receiving the sound signal through the sound receiver, and according to the similarity/difference of the two detection results, the determination threshold is corrected in the case of passively receiving the sound signal, so that the to-be-adjusted detection result is determined to be consistent with the first detection result.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A critical data display process includes a computer directing a medical testing result for a patient to appear on a health care practitioner critical data display of a health care practitioner display monitor of a single health care practitioner. The process also includes the computer prompting the single health care practitioner through the health care practitioner critical data display to review the medical testing result for the patient on the health care practitioner critical data display, to designate or accept a previous designation of the medical testing result as either critical or noncritical, and to enter or authorize patient instructions. The process further includes the computer directing a patient critical data display to appear on a patient display monitor of a patient representative of the patient.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device includes a first dielectric layer, a cobalt-containing conductive feature, a non-cobalt conductive feature, a second dielectric layer, a first tungsten contact feature, a second tungsten contact feature, and a tungsten barrier layer. The cobalt-containing conductive feature is disposed in the first dielectric layer. The non-cobalt conductive feature is disposed in the first dielectric layer, and is spaced apart from the cobalt-containing conductive feature. The second dielectric layer is disposed over the first dielectric layer. The first tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the cobalt-containing conductive feature. The second tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the non-cobalt conductive feature.

Abstract: The present disclosure describes semiconductor devices and methods for forming the same. A method for forming a semiconductor device includes forming a source/drain structure and forming a gate structure. The method also includes performing a cleaning process on the source/drain structure and the gate structure. The method also includes disposing a portion of a byproduct of the cleaning process on a top surface of the gate structure and etching the portion of the byproduct so a remaining portion of the byproduct is formed on the top surface of the gate structure. The method further includes forming a gate contact structure, including depositing a metal material on the remaining portion of the byproduct to form a compound containing the metal material and the remaining portion of the byproduct. The method also includes forming a barrier layer between the compound and the top surface of the gate structure.

Abstract: A method for correcting a determination threshold of a floor medium and a method of detecting thereof are provided. The method is used for controlling a mobile robot equipped with a sound emitter and a sound receiver to detect and recognize the floor medium during a movement just started. A first detection result of a current floor medium is obtained by actively transmitting and receiving a sound signal, then, a to-be-adjusted detection result of the current floor medium is obtained only by passively receiving the sound signal through the sound receiver, and according to the similarity/difference of the two detection results, the determination threshold is corrected in the case of passively receiving the sound signal, so that the to-be-adjusted detection result is determined to be consistent with the first detection result.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device includes a first dielectric layer, a cobalt-containing conductive feature, a non-cobalt conductive feature, a second dielectric layer, a first tungsten contact feature, a second tungsten contact feature, and a tungsten barrier layer. The cobalt-containing conductive feature is disposed in the first dielectric layer. The non-cobalt conductive feature is disposed in the first dielectric layer, and is spaced apart from the cobalt-containing conductive feature. The second dielectric layer is disposed over the first dielectric layer. The first tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the cobalt-containing conductive feature. The second tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the non-cobalt conductive feature.

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.