Patents by Inventor Li Yu

Li Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10546186
    Abstract: A method and system using face tracking and object tracking is disclosed. The method and system use face tracking, location, and/or recognition to enhance object tracking, and use object tracking and/or location to enhance face tracking.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 28, 2020
    Assignee: AVIGILON FORTRESS CORPORATION
    Inventors: Paul C. Brewer, Dana Eubanks, Himaanshu Gupta, W. Andrew Scanlon, Peter L. Venetianer, Weihong Yin, Li Yu, Zhong Zhang
  • Publication number: 20200026925
    Abstract: Embodiments of the present disclosure provide a method and a device for generating an electronic map, an electronic device, a computer readable storage medium, and an acquisition entity. The method includes: obtaining a first point cloud sequence and a second point cloud sequence for a preset region; generating a first grid map for the first point cloud sequence and a second grid map for the second point cloud sequence, wherein a grid in each of the first grid map and the second grid map at least comprises reflection value information of a point cloud; and optimizing the first point cloud sequence based on the first grid map and the second grid map.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 23, 2020
    Inventors: Li YU, Shiyu SONG
  • Patent number: 10541094
    Abstract: A medium or low voltage circuit interrupter includes a housing with a first end cap, a second end cap that comprises a radial bellows, and one or more insulating sidewalls that extends from the first end cap to the second end cap. The end caps and one or more sidewalls provide a vacuum chamber. A fixed contact that extends through an opening of the first end cap and into the vacuum chamber. A moveable contact that extends through an opening of the second end cap and into the vacuum chamber. Multiple such interrupters may be electrically connected in series, positioned a single plane, and actuated by a single actuator.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 21, 2020
    Assignee: Eaton Intelligent Power Limited
    Inventors: Li Yu, Mark A. Juds, Paul J. Rollmann, Andrew A. Rockhill, Hongbin Wang
  • Patent number: 10533978
    Abstract: A component monitoring system structured to monitor circuit breaker assembly component characteristics is provided. The component monitoring system includes a record assembly, a number of vibration sensor assemblies, a comparison assembly, and an output assembly. The record assembly includes selected nominal data for a selected circuit breaker component. The vibration sensor assembly is structured to measure a number of actual component characteristics for a substantial portion of the circuit breaker assembly and to transmit actual component characteristic output data. The comparison assembly is structured to receive an electronic signal from said record assembly and said sensor assemblies, to compare each sensor assembly actual component characteristic output data to said selected nominal data and to provide an indication signal as to whether said sensor assembly output data is acceptable when compared to the selected nominal data. The output assembly includes a communication assembly and an output device.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: January 14, 2020
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: James Jeffery Benke, Koustubh Dnyandeo Ashtekar, Li Yu, Jiong Chen, Fangji Wu, He Yang, Wilbert deVries
  • Publication number: 20200011675
    Abstract: Embodiments of the present disclosure provide a method and a device for acquiring a map, a device, and a computer readable storage medium. The method includes: acquiring a reference map of an acquisition area; dividing the acquisition area into a plurality of sub-areas based on the reference map; generating a plurality of acquisition tasks corresponding to the plurality of sub-areas, wherein each of the plurality of acquisition tasks is configured to acquire a map of each of the plurality of sub-areas; and assigning each of the plurality of acquisition tasks to an acquisition entity, to enable the acquisition entity to acquire the map of each of the plurality of sub-areas.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Inventors: Li YU, Shiyu SONG, Fangfang DONG
  • Patent number: 10521529
    Abstract: A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 31, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20190384868
    Abstract: A method and apparatus for adaptive voltage scaling to eliminate delay variation of a whole design are provided. The method may include: reading a circuit simulation netlist file, a circuit design database, and a path list; building a delay variation database of each minimum unit within multiple minimum units of the whole design under various voltage levels according to the circuit design database; utilizing an initial voltage level to be a voltage level of a driving voltage of the whole design to apply the initial voltage level to the whole design, and performing static timing analysis (STA) on the whole design, to determine whether any timing violation path exists in the path list; and selectively adjusting the voltage level of the driving voltage and re-performing the STA until no timing violation path exists.
    Type: Application
    Filed: March 17, 2019
    Publication date: December 19, 2019
    Inventors: Mei-Li Yu, Ying-Chieh Chen, Yu-Lan Lo, Hsin-Chang Lin, Shu-Yi Kao
  • Publication number: 20190371044
    Abstract: Embodiments of the present disclosure relate to a method, apparatus, device and computer readable storage medium for reconstructing a three-dimensional scene. The method for reconstructing a three-dimensional scene includes acquiring a point cloud data frame set for a three-dimensional scene, point cloud data frames in the point cloud data frame set respectively having a pose parameter. The method further comprises determining a subset corresponding to a part of the three-dimensional scene from the point cloud data frame set. The method further comprises adjusting a pose parameter of a point cloud data frame in the subset to obtain an adjusted subset, the adjusted subset including at least two point cloud data frames having matching overlapping parts. The method further comprises updating the point cloud data frame set using the adjusted subset. In this way, distributed processing on a large amount of point cloud data may be realized.
    Type: Application
    Filed: March 14, 2019
    Publication date: December 5, 2019
    Inventors: Li YU, Shiyu SONG
  • Patent number: 10490363
    Abstract: An electrical contact for a vacuum switching apparatus. The vacuum switching apparatus includes a second electrical contact. The electrical contact includes a hub portion and a plurality of petal portions each extending from the hub portion. Each of the plurality of petal portions has a first surface and a second surface. The first surface faces in a first direction and is structured to engage the second electrical contact. The second surface faces in a second direction generally opposite the first direction. At least one of the plurality of petal portions further has a grooved portion extending inwardly from the second surface toward the first surface.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: November 26, 2019
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Wangpei Li, Li Yu, Somasundara Rao Matu
  • Publication number: 20190348362
    Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 14, 2019
    Inventors: Yu-Bey WU, Dian-Hau CHEN, Jye-Yen CHENG, Sheng-Hsuan WEI, Li-Yu LEE, Tai-Yang WU
  • Publication number: 20190348963
    Abstract: A bulk acoustic wave (BAW) resonator is disclosed. The BAW resonator includes: a lower electrode; a piezoelectric layer disposed over the lower electrode; and an upper electrode over the piezoelectric layer. An opening having a first area exists in and extends completely through the upper electrode. The BAW resonator also includes a substrate disposed below the lower electrode; a cavity; and a pillar disposed in the cavity and extending to contact a portion of the lower electrode disposed beneath the opening. The pillar has a second area that is less than the first area. There are no electrical connections that extend across the opening from one side to another.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Brice Ivira, Chris Kirkendall, Pen Li Yu, Sormeh Setoodeh, David Albert Feld
  • Publication number: 20190323843
    Abstract: The present disclosure provides a method and an apparatus for generating a high precision map, and a storage medium for generating a high precision map. The method includes: performing a point cloud splicing process on target point cloud data to obtain a lidar pose corresponding to the target point cloud data; projecting the target point cloud data into a preset two-dimensional area based on the lidar pose to generate a map based on a reflection value and a height value; performing a self-positioning verification on the map based on the reflection value and the height value using the target point cloud data; and integrating, if a result of the self-positioning verification satisfies a preset condition, the map based on the reflection value and the height value into a reference map to generate the high precision map. The present disclosure can obtain a high precision map with a wider application range.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Li YU, Shiyu SONG, Fangfang DONG
  • Patent number: 10444431
    Abstract: A reticulated resonator includes: a reticulated substrate that includes: a substrate frame; and a phononic structure in mechanical communication with the substrate frame and including a plurality of unit members arranged in a two-dimensional array; and a membrane disposed on the reticulated substrate.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: October 15, 2019
    Assignee: NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY
    Inventors: Raymond W. Simmonds, Katarina Cicak, Cindy A. Regal, Pen-Li Yu, Yeghishe Tsaturyan, Thomas P. Purdy, Nir S. Kampel
  • Patent number: 10424444
    Abstract: A failure prediction assembly is structured to monitor circuit breaker assembly sub-assemblies and their component's characteristics. The failure prediction assembly includes a sensor supported D-shaft and a sensor assembly including a housing and a number of sensors. The sensor assembly housing defines a D-shaft passage. A control unit is in electronic communication with the sensor assembly. The sensor assembly housing is coupled to the circuit breaker sidewalls with the sensor assembly housing D-shaft passage aligned with the circuit breaker sidewall D-shaft passages. The sensor supported D-shaft is rotatably coupled to the sensor assembly with the sensor supported D-shaft disposed through said sensor assembly housing D-shaft passage.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 24, 2019
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: He Yang, Chao Xin, Jiong Chen, Mark Mao, Li Yu
  • Patent number: 10425638
    Abstract: The present invention is to provide an image processing equipment and method, for enabling an electronic device having a plurality of image capturing elements installed thereon to capture calibration sample images of a parameter calibration module and verification sample images of a parameter verification module, wherein the parameter calibration module is formed by four calibration identification boards each having a chess board pattern printed thereon and arranged parallelly in a predetermined angle with each other, the parameter verification module is formed by four verification identification boards each having a chess board pattern printed thereon and arranged in parallel with each other, so as for the electronic device to promptly calibrate the intrinsic and extrinsic parameters of the mage capturing elements according to the calibration sample images and then to promptly verify the correctness of the calibrated intrinsic and extrinsic parameters according to the verification sample images.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 24, 2019
    Assignee: MULTIMEDIA IMAGE SOLUTION LIMITED
    Inventors: Li Yu, Wang Miao, Jian-Hua Lin, Jin Wang
  • Publication number: 20190275139
    Abstract: A temperature-sensitive attenuated FMDV strain, construction method and applications thereof. The construction method of the temperature-sensitive attenuated FMDV strain is as follows. Mutating a cytosine on K region loop of IRES domain 4 of an FMDV genome to a guanine or an adenine to obtain the temperature-sensitive attenuated FMDV strain, or replacing a K region of IRES domain 4 of an FMDV genome with a K region of IRES domain 4 of a bovine rhinovirus genome to obtain the temperature-sensitive attenuated FMDV strain.
    Type: Application
    Filed: November 20, 2017
    Publication date: September 12, 2019
    Applicant: HARBIN VETERINARY RESEARCH INSTITUTE, CHINESE ACADEMY OF AGRICULTURAL SCIENCES
    Inventors: Li YU, Decheng YANG, Haiwei WANG, Guohui ZHOU
  • Patent number: 10402999
    Abstract: The present disclosure discloses a method, apparatus and server for constructing a map. An embodiment of the method comprises: building a point cloud data frame sequence using point cloud data frames acquired in real time; extracting morphological data from the point cloud data frames; establishing a spatial position relation between the morphological data of two adjacent point cloud data frames in the point cloud data frame sequence; determining a reference spatial position relation corresponding to a stationary object based on the spatial position relation, and constructing a map with the reference spatial position relation. The present embodiment realizes constructing a map with the point cloud data.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: September 3, 2019
    Assignee: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) Co., LTD
    Inventors: Shichun Yi, Cheng Wang, Li Yu, Shiyu Song, Fangfang Dong
  • Publication number: 20190251537
    Abstract: Methods and systems are provided for monitoring a point of sale (POS) transaction. Operations performed by the methods and systems include generating POS primitives by processing non-video data of a transaction recorded at POS terminal. The operations also include generating video primitives by processing video data of the transaction recorded at the POS terminal. The operations further include determining that the transaction comprises an exceptional transaction by comparing the non-video data and/or the video data to exceptional transaction rules. Additionally, the operations include determining that the exceptional transaction comprises a verified exceptional transaction by generating a video event based on the video primitives and a corresponding video rule.
    Type: Application
    Filed: December 28, 2018
    Publication date: August 15, 2019
    Inventors: Alan J. Lipton, Peter L. Venetianer, Li Yu, Yongtong Hu, W. Andrew Scanlon, Zhong Zhang, Weihong Yin
  • Publication number: 20190246073
    Abstract: A system for detecting behavior of a target may include: a target detection engine, adapted to detect at least one target from one or more objects from a video surveillance system recording a scene; a path builder, adapted to create at least one mature path model from analysis of the behavior of a plurality of targets in the scene, wherein the at least one mature path model includes a model of expected target behavior with respect to the at least one path model; and a target behavior analyzer, adapted to analyze and identify target behavior with respect to the at least one mature path model. The system may further include an alert generator, adapted to generate an alert based on the identified behavior.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Niels HAERING, Zeeshan RASHEED, Li YU, Andrew J. CHOSAK
  • Patent number: 10361156
    Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Bey Wu, Dian-Hau Chen, Jye-Yen Cheng, Sheung-Hsuan Wei, Li-Yu Lee, Tai-Yang Wu