Patents by Inventor Lian-Chun Lee

Lian-Chun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11789659
    Abstract: A method for dynamically managing host read operation and read refresh operation in a storage device, a storage device and a storage medium thereof are provided. The method includes: controlling, by a controller of the storage device, a ratio of the number of host read operation to the number of read refresh operation in the storage device to be in line with a first value and obtaining a total read request count which accumulates in the storage device; when a criterion for updating the ratio is satisfied, determining, by the controller, a second value for the ratio of the number of host read operation to the number of read refresh operation according to the total read request count and information of blocks to be refreshed in the storage device; and controlling, by the controller, the number of host read operation and the number of read refresh operation so that a ratio of the number of host read operation to the number of read refresh operation is in line with the second value.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: October 17, 2023
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee, Chun-Shu Chen
  • Patent number: 11687275
    Abstract: A method for assigning a plurality of channel of a storage device for stream data writing, a storage device and a storage medium are provided. The method includes: providing global available channel status data and stream suitable channel status data for one of a plurality of streams by a controller of the storage device for processing stream data writing for the plurality of streams; generating stream available channel status data for the one of the plurality of streams, based on the global available channel status data and the stream suitable channel status data for the stream; selecting at least one available channel of the plurality of channels according to the stream available channel status data; and updating the global available channel status data with respect to the at least one available channel selected and updating the stream suitable channel status data for one of the plurality of streams.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: June 27, 2023
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee, Chun-Shu Chen
  • Publication number: 20230185488
    Abstract: A method for dynamically managing host read operation and read refresh operation in a storage device, a storage device and a storage medium thereof are provided. The method includes: controlling, by a controller of the storage device, a ratio of the number of host read operation to the number of read refresh operation in the storage device to be in line with a first value and obtaining a total read request count which accumulates in the storage device; when a criterion for updating the ratio is satisfied, determining, by the controller, a second value for the ratio of the number of host read operation to the number of read refresh operation according to the total read request count and information of blocks to be refreshed in the storage device; and controlling, by the controller, the number of host read operation and the number of read refresh operation so that a ratio of the number of host read operation to the number of read refresh operation is in line with the second value.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 15, 2023
    Applicant: SK hynix Inc.
    Inventors: CHING-CHUNG LAI, LIAN-CHUN LEE, CHUN-SHU CHEN
  • Patent number: 11513949
    Abstract: The memory system comprises nonvolatile memory devices each including plural superblocks and a controller. The controller is configured to select a victim superblock including a smaller number of valid pages than any among remaining superblocks, exchange a greater-valid-pages block with a smaller-valid-pages block, and control the memory device to perform a garbage collection operation on the victim superblock, wherein the greater-valid-pages block is included in the victim superblock and the smaller-valid-pages block is included in one among the remaining superblocks, and wherein the smaller-valid-pages block has a smaller number of valid pages than the greater-valid-pages block.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee, Chun-Shu Chen
  • Publication number: 20220197543
    Abstract: A method for assigning a plurality of channel of a storage device for stream data writing, a storage device and a storage medium are provided. The method includes: providing global available channel status data and stream suitable channel status data for one of a plurality of streams by a controller of the storage device for processing stream data writing for the plurality of streams; generating stream available channel status data for the one of the plurality of streams, based on the global available channel status data and the stream suitable channel status data for the stream; selecting at least one available channel of the plurality of channels according to the stream available channel status data; and updating the global available channel status data with respect to the at least one available channel selected and updating the stream suitable channel status data for one of the plurality of streams.
    Type: Application
    Filed: November 18, 2021
    Publication date: June 23, 2022
    Applicant: SK hynix Inc.
    Inventors: CHING-CHUNG LAI, LIAN-CHUN LEE, CHUN-SHU CHEN
  • Publication number: 20220100650
    Abstract: The memory system comprises nonvolatile memory devices each including plural superblocks and a controller. The controller is configured to select a victim superblock including a smaller number of valid pages than any among remaining superblocks, exchange a greater-valid-pages block with a smaller-valid-pages block, and control the memory device to perform a garbage collection operation on the victim superblock, wherein the greater-valid-pages block is included in the victim superblock and the smaller-valid-pages block is included in one among the remaining superblocks, and wherein the smaller-valid-pages block has a smaller number of valid pages than the greater-valid-pages block.
    Type: Application
    Filed: March 24, 2021
    Publication date: March 31, 2022
    Inventors: Ching-Chung LAI, Lian-Chun LEE, Chun-Shu CHEN
  • Patent number: 11068189
    Abstract: A control method of a storage device may include the steps of determining, by a storage device controller of the storage device, whether the storage device has to move internal data; deciding, by the storage device controller, a data movement allocation ratio based on at least some of internal data movement requests and the number of free pages in the storage device, when it is determined that the storage device has to move internal data; and allocating, by the storage device controller, one or more programming times to complete a first data number of internal data movement operations corresponding to at least some of the internal data movement requests and a second data number of host data write operations, such that the ratio of the first and second data numbers coincides with the data movement allocation ratio.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: July 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee, Chun-Shu Chen
  • Patent number: 11036437
    Abstract: A control method of a storage device wherein a host cannot transfer a command to the storage device when the storage device transfers data to the host, after which there is a data transfer delay time period and no data is transferred to the host until a read command is received from the host, the control method comprising the steps of: detecting, by a memory controller of the storage device, a host delay time of the host each time a read command is received from the host during the data transfer delay time period; and adjusting, by the memory controller, the data transfer delay time period based on one or more of the detected host delay times.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Chun-Shu Chen, Lian-Chun Lee, Ching-Chung Lai
  • Publication number: 20200326874
    Abstract: A control method of a storage device may include the steps of determining, by a storage device controller of the storage device, whether the storage device has to move internal data; deciding, by the storage device controller, a data movement allocation ratio based on at least some of internal data movement requests and the number of free pages in the storage device, when it is determined that the storage device has to move internal data; and allocating, by the storage device controller, one or more programming times to complete a first data number of internal data movement operations corresponding to at least some of the internal data movement requests and a second data number of host data write operations, such that the ratio of the first and second data numbers coincides with the data movement allocation ratio.
    Type: Application
    Filed: November 5, 2019
    Publication date: October 15, 2020
    Inventors: Ching-Chung LAI, Lian-Chun LEE, Chun-Shu CHEN
  • Patent number: 10754786
    Abstract: A memory access method for selectively creating a simplified mapping table includes the steps of: selecting one of a plurality of partitions of an original mapping table so as to use one physical page address in a selected partition as a start physical page address; scanning each entry of the selected partition so as to search a randomly mapped entry in the selected partition; determining whether a memory space required for creating the simplified mapping table is smaller than a memory space required for the selected partition; and selectively storing the start physical page address, the number of the randomly mapped entries, and a logical page address and a physical page address recorded on each randomly mapped entry according to the determination result of the determining step so as to create a simplified mapping table.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee
  • Publication number: 20200233611
    Abstract: A control method of a storage device wherein a host cannot transfer a command to the storage device when the storage device transfers data to the host, after which there is a data transfer delay time period and no data is transferred to the host until a read command is received from the host, the control method comprising the steps of: detecting, by a memory controller of the storage device, a host delay time of the host each time a read command is received from the host during the data transfer delay time period; and adjusting, by the memory controller, the data transfer delay time period based on one or more of the detected host delay times.
    Type: Application
    Filed: October 21, 2019
    Publication date: July 23, 2020
    Inventors: Chun-Shu CHEN, Lian-Chun LEE, Ching-Chung LAI
  • Publication number: 20190361627
    Abstract: A control method of a memory device may include: (a) reading a read request of a host; (b) determining, by the processor, whether a logical address corresponding to the read request of the host is present in a cache; and (c) generating, by the processor, a data read command according the read request when the determination result of (b) indicates that the logical address corresponding to the read request is present in the cache, and transferring, by the processor, the data read command to one of the plurality of memory channels which corresponds to the physical address, in order to process the data read command.
    Type: Application
    Filed: March 19, 2019
    Publication date: November 28, 2019
    Inventors: Ching-Chung LAI, Lian-Chun LEE
  • Publication number: 20190236021
    Abstract: A memory access method for selectively creating a simplified mapping table includes the steps of: selecting one of a plurality of partitions of an original mapping table so as to use one physical page address in a selected partition as a start physical page address; scanning each entry of the selected partition so as to search a randomly mapped entry in the selected partition; determining whether a memory space required for creating the simplified mapping table is smaller than a memory space required for the selected partition; and selectively storing the start physical page address, the number of the randomly mapped entries, and a logical page address and a physical page address recorded on each randomly mapped entry according to the determination result of the determining step so as to create a simplified mapping table.
    Type: Application
    Filed: December 4, 2018
    Publication date: August 1, 2019
    Inventors: Ching-Chung LAI, Lian-Chun LEE
  • Patent number: 9830282
    Abstract: An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a command signal and creates data transmission link to the computer device. The master storage unit has at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to transmit the command signal from the master storage unit to the slave storage unit.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 28, 2017
    Assignee: SK hynix Inc.
    Inventor: Lian Chun Lee
  • Patent number: 9804799
    Abstract: Disclosed are a memory storage device and an operating method thereof. The operating method writes data to a plurality of memory devices of the memory storage device through a controller, and performs interleaving programming on the plurality of memory devices. The operating method includes a write request step, a read request step, a page temporary storage area write step, and a device switching step, which are repeated until the respective memory devices complete the above-described steps and a page temporary storage area programming step. Before the page temporary storage area programming step is performed, data transmitted to page temporary storage areas of the respective memory devices are temporarily stored in the page temporary storage areas. Thus, the number of SRAMs can be, reduced, and a programming operation can be performed on a plurality of memory devices at the same time.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 31, 2017
    Assignee: SK Hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee
  • Publication number: 20170168754
    Abstract: Disclosed are a memory storage device and an operating method thereof. The operating method writes data to a plurality of memory devices of the memory storage device through a controller, and performs interleaving programming on the plurality of memory devices. The operating method includes a write request step, a read request step, a page temporary storage area write step, and a device switching step, which are repeated until the respective memory devices complete the above-described steps and a page temporary storage area programming step. Before the page temporary storage area programming step is performed, data transmitted to page temporary storage areas of the respective memory devices are temporarily stored in the page temporary storage areas. Thus, the number of SRAMs can be, reduced, and a programming operation can be performed on a plurality of memory devices at the same time.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 15, 2017
    Inventors: Ching-Chung LAI, Lian-Chun LEE
  • Publication number: 20170010990
    Abstract: An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a command signal and creates data transmission link to the computer device. The master storage unit has at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to transmit the command signal from the master storage unit to the slave storage unit.
    Type: Application
    Filed: September 21, 2016
    Publication date: January 12, 2017
    Inventor: Lian Chun LEE
  • Patent number: 9471529
    Abstract: An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 18, 2016
    Assignee: SK hynix Inc.
    Inventor: Lian Chun Lee
  • Publication number: 20150149674
    Abstract: An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: SK hynix Inc.
    Inventor: Lian Chun LEE
  • Publication number: 20110296081
    Abstract: A data access method and a related control system are provided according to embodiments of the present invention, which enhances the read/write performance of a data storage unit by performing pre-accessing operations upon the data storage unit. The data access method includes receiving a plurality of access requests and a plurality of corresponding addresses to access a plurality of data corresponding to the plurality of access requests from a storage unit; and performing a pre-accessing operation upon the storage unit according to the uniformity of the plurality of access requests and the continuity between the plurality of addresses.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 1, 2011
    Inventors: Chia-Jung Hsu, Lian-Chun Lee, Kun-Pin Lai