Abstract: An anti-CD33 antibody and a preparation method therefor and an application thereof. The anti-CD33 antibody has high affinity with CD33 protein, and therefore, can be used for preparation of a drug for treating tumor and the like.

Abstract: Currency note sorting devices and systems, and corresponding methods of identifying and sorting currency notes are described herein. A method for sorting currency notes that includes receiving currency notes, identifying the denomination of the currency notes, and distributing the currency notes to slots of a wallet based on the identified denomination. The wallet slots include staggered braille tabs to aid visual-impaired users of the wallet.

Abstract: Currency note sorting devices and systems, and corresponding methods of identifying and sorting currency notes are described herein. A method for sorting currency notes that includes receiving currency notes, identifying the denomination of the currency notes, and distributing the currency notes to slots of a wallet based on the identified denomination. The wallet slots include staggered braille tabs to aid visual-impaired users of the wallet.

Abstract: A method of dissolving cellulose, comprising: firstly heating and activating the cellulose by using a heating apparatus, and then dissolving by using a solvent. The temperature of the heating and the activating is 130° C.-270° C., the time period of the heating is 0.1-100 hours, and the solvent is an aqueous solution including 6 wt %-12 wt % sodium hydroxide and 0.1 wt %-6 wt % zinc oxide. The method of dissolving comprises: heating and activating the cellulose with a degree of polymerization of DP=300-700, dispersing the cellulose into the solvent, and freezing under a temperature of ?10˜-30° C. for 0.1-50 hours; then unfreezing under a condition of no more than 32° C., and standing or stirring by machine during the process of unfreezing so as to dissolve and obtain a cellulose solution with a concentration of 3 wt %-12 wt %. The obtained cellulose solution has a good solubility and stability that maintains a relatively good stability after being stood under a temperature of ?8 to 32° C. for a few days.

Abstract: According to some embodiments, systems and methods are provided to link a first entry point of a first kernel to a dummy entry, link a second entry point of a second kernel to the dummy entry, and compile the first kernel and the second kernel.

Abstract: Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.

Abstract: The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period.

Abstract: Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.

Abstract: The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period.

Abstract: According to some embodiments, systems and methods are provided to link a first entry point of a first kernel to a dummy entry, link a second entry point of a second kernel to the dummy entry, and compile the first kernel and the second kernel.