Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a system includes a first graphics processing unit, a second graphics processing unit and a central processing unit. The first graphics processing unit processes a first data block of a data matrix associated with a matrix factorization system to generate first information for the matrix factorization system. The second graphics processing unit processes a first portion of a second data block of the data matrix separate from a second portion of the second data block to generate second information for the matrix factorization system. The central processing unit processes a machine learning model for the matrix factorization system based on at least the first information provided by the first graphics processing unit and the second information provided by the second graphics processing unit.

Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a system includes a first graphics processing unit, a second graphics processing unit and a central processing unit. The first graphics processing unit processes a first data block of a data matrix associated with a matrix factorization system to generate first information for the matrix factorization system. The second graphics processing unit processes a first portion of a second data block of the data matrix separate from a second portion of the second data block to generate second information for the matrix factorization system. The central processing unit processes a machine learning model for the matrix factorization system based on at least the first information provided by the first graphics processing unit and the second information provided by the second graphics processing unit.

Abstract: A random binning featurization process method, system, and computer program product for a distributed random binning featurization process on one or more multicore systems with a hybrid two-level parallelism, the method including in a training phase, receiving a first data matrix dividing the random binning featurization process into two orthogonal levels, in a high-level generating a randomized number of high-dimension grids and evenly partitioning the grids into nodes in a parallel system, and in a low-level, evenly partitioning dimensions in each grid to construct look-up tables of index vectors and compute a local feature matrix for each node.

Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a system includes a first graphics processing unit, a second graphics processing unit and a central processing unit. The first graphics processing unit processes a first data block of a data matrix associated with a matrix factorization system to generate first information for the matrix factorization system. The second graphics processing unit processes a first portion of a second data block of the data matrix separate from a second portion of the second data block to generate second information for the matrix factorization system. The central processing unit processes a machine learning model for the matrix factorization system based on at least the first information provided by the first graphics processing unit and the second information provided by the second graphics processing unit.

Abstract: A workload scheduling method, system, and computer program product include analyzing a resource scheduling requirement for processes of a workload including the communication patterns among CPUs and accelerators, creating feasible resources based on static resource information of the resources for the processes of the workload, and selecting an available resource of the feasible resources to assign the workload based on the resource scheduling requirement, such that the CPU and GPU connection topology of the selection matches the communication patterns of the workload.

Abstract: A block coordinate descent method, system, and computer program product for partitioning a global feature matrix into blocks, each node of the nodes of the blocks having a block size of a number of the blocks over a number of the nodes, selecting, at each node, a subset of the blocks from the blocks, and in one of the nodes, launching a thread to simultaneously update a closed-form solution by minimizing a single coordinate in one of the blocks.

Abstract: A topology-aware parallel reduction method, system, and recording medium including obtaining the GPU connection topology of each of the plurality of GPUs as a connection tree, transforming the connection tree into a three layer tree comprising an intra-root tree, an intra-node tree, and an inter-node tree, evenly partitioning each entry on each of the GPUS, and selectively transferring data either in either direction or in each direction, simultaneously, along the evenly partitioned three layer tree using a full-duplex configuration of a PCIe bandwidth.

Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a system includes a first graphics processing unit, a second graphics processing unit and a central processing unit. The first graphics processing unit processes a first data block of a data matrix associated with a matrix factorization system to generate first information for the matrix factorization system. The second graphics processing unit processes a first portion of a second data block of the data matrix separate from a second portion of the second data block to generate second information for the matrix factorization system. The central processing unit processes a machine learning model for the matrix factorization system based on at least the first information provided by the first graphics processing unit and the second information provided by the second graphics processing unit.

Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a system includes a first graphics processing unit, a second graphics processing unit and a central processing unit. The first graphics processing unit processes a first data block of a data matrix associated with a matrix factorization system to generate first information for the matrix factorization system. The second graphics processing unit processes a first portion of a second data block of the data matrix separate from a second portion of the second data block to generate second information for the matrix factorization system. The central processing unit processes a machine learning model for the matrix factorization system based on at least the first information provided by the first graphics processing unit and the second information provided by the second graphics processing unit.

Abstract: A topology-aware parallel reduction method, system, and recording medium including obtaining the GPU connection topology of each of the plurality of GPUs as a connection tree, transforming the connection tree into a three layer tree comprising an intra-root tree, an intra-node tree, and an inter-node tree, evenly partitioning each entry on each of the GPUS, and selectively transferring data either in either direction or in each direction, simultaneously, along the evenly partitioned three layer tree using a full-duplex configuration of a PCIe bandwidth.

Abstract: A topology-aware parallel reduction method, system, and recording medium including a partitioning device configured to partition data in each accelerator of a plurality of accelerators into partitions based on a topology of connections between the plurality of accelerators and a control device configured to control, based on a topology of connections between the plurality of accelerators, a type of parallel reduction of data to use.

Abstract: A workload scheduling method, system, and computer program product include analyzing a resource scheduling requirement for processes of a workload including the communication patterns among CPUs and accelerators, creating feasible resources based on static resource information of the resources for the processes of the workload, and selecting an available resource of the feasible resources to assign the workload based on the resource scheduling requirement, such that the CPU and GPU connection topology of the selection matches the communication patterns of the workload.

Abstract: A block coordinate descent method, system, and computer program product for partitioning a global feature matrix into blocks, each node of the nodes of the blocks having a block size of a number of the blocks over a number of the nodes, selecting, at each node, a subset of the blocks from the blocks, and in one of the nodes, launching a thread to simultaneously update a closed-form solution by minimizing a single coordinate in one of the blocks.

Abstract: A random binning featurization process method, system, and computer program product for a distributed random binning featurization process on one or more multicore systems with a hybrid two-level parallelism, the method including in a training phase, receiving a first data matrix dividing the random binning featurization process into two orthogonal levels, in a high-level generating a randomized number of high-dimension grids and evenly partitioning the grids into nodes in a parallel system, and in a low-level, evenly partitioning dimensions in each grid to construct look-up tables of index vectors and compute a local feature matrix for each node.

Abstract: A method and structure for dynamic memory re-allocation for an application runtime environment (ARE) includes receiving, through an interface of an application runtime environment (ARE), a first set of internal operational metrics of the ARE executing at a current setting S1 on a processor of a computer. A first performance P1 of the ARE is determined at the current setting S1 using the received first set of internal operation metrics. The current setting S1 of the ARE is varied to a new setting S2. A second set of internal operational metrics of the ARE executing at the new setting S2 is received through the interface of the ARE. A second performance P2 of the ARE is determined at the new setting S2, using the received second set of internal operation metrics. A memory allocation for the ARE is re-allocated, based on the determined performances P1 and P2.

Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a system includes a first graphics processing unit, a second graphics processing unit and a central processing unit. The first graphics processing unit processes a first data block of a data matrix associated with a matrix factorization system to generate first information for the matrix factorization system. The second graphics processing unit processes a first portion of a second data block of the data matrix separate from a second portion of the second data block to generate second information for the matrix factorization system. The central processing unit processes a machine learning model for the matrix factorization system based on at least the first information provided by the first graphics processing unit and the second information provided by the second graphics processing unit.

Abstract: An apparatus includes at least one processor executing a method for managing memory among a plurality of concurrently-running virtual machines, and a non-transitory memory device that stores a set of computer readable instructions for implementing and executing said memory management method. A memory optimization mechanism can reduce a memory usage of a virtual machine at a cost of increasing a central processing unit (CPU) usage. Information on a memory usage and a CPU usage of each virtual machine is periodically collected. When a first virtual machine exhibits high memory use, at least one second virtual machine with an extra CPU capacity is identified. A memory optimization mechanism is applied to the second virtual machine to reduce memory used by the second virtual machine, thereby providing a portion of freed memory that is then allocated to the first virtual machine.

Abstract: A topology-aware parallel reduction method, system, and recording medium including a partitioning device configured to partition data in each accelerator of a plurality of accelerators into partitions based on a topology of connections between the plurality of accelerators and a control device configured to control, based on a topology of connections between the plurality of accelerators, a type of parallel reduction of data to use.

Abstract: A method and structure for dynamic memory re-allocation for an application runtime environment (ARE) includes receiving, through an interface of an application runtime environment (ARE), a first set of internal operational metrics of the ARE executing at a current setting S1 on a processor of a computer. A first performance P1 of the ARE is determined at the current setting S1 using the received first set of internal operation metrics. The current setting S1 of the ARE is varied to a new setting S2. A second set of internal operational metrics of the ARE executing at the new setting S2 is received through the interface of the ARE. A second performance P2 of the ARE is determined at the new setting S2, using the received second set of internal operation metrics. A memory allocation for the ARE is re-allocated, based on the determined performances P1 and P2.

Abstract: A method and structure for dynamic memory re-allocation for an application runtime environment (ARE) includes receiving, through an interface of an application runtime environment (ARE), a first set of internal operational metrics of the ARE executing at a current setting S1 on a processor of a computer. A first performance P1 of the ARE is determined at the current setting S1 using the received first set of internal operation metrics. The current setting S1 of the ARE is varied to a new setting S2. A second set of internal operational metrics of the ARE executing at the new setting S2 is received through the interface of the ARE. A second performance P2 of the ARE is determined at the new setting S2, using the received second set of internal operation metrics. A memory allocation for the ARE is re-allocated, based on the determined performances P1 and P2.