Abstract: A method of detecting PN code synchronization for a DSSS signal comprising receiving a DSSS data signal of data frames comprised of I and Q symbols, at least a portion of each data frame comprising a unique word, demodulating the data signal into I and Q chip samples, filtering the I and Q chip samples and outputting the filtered I and Q chip samples to a chip stream controller which outputs the plurality of chip streams to a correlation matrix that correlates the plurality of chip streams with the chipped unique word and outputs a correlated data stream. A plurality of FFTs is run on the correlated output data stream and a processor searches for a maximum frequency bin power of each FFT. A PN synchronization detector searches for a maximum frequency bin power of each FFT. A PN synchronization detector searches for a maximum frequency bin power among the plurality of FFT rounds and determines whether PN synchronization is present.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: Time delay and frequency offset calculation systems and related methods. System implementations include modules coupled together configured to calculate a time delay and a corresponding frequency offset of a second signal delayed in time relative to a first signal with the maximum value of a magnitude of a delay optimization function. Implementations of a method for calculating a time delay and frequency offset calculate the maximum value of the delay optimization function by generating the cross-correlation of one or more adjacent discrete Fourier transformed blocks corresponding to the first signal and second signal, respectively, of two or more discrete Fourier transformed blocks. The maximum value of the delay optimization function is then identified. Implementations of the method may compare the identified maximum value of the magnitude of the delay optimization function with a threshold to determine whether to continue processing for additional adjacent discrete Fourier transformed blocks.

Abstract: A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (ISDC) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (DPLL) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (AGC) that maintains near full scale operation of adaptive filtering and the DPLL, and a slicer, mixer, and delay unit forming an error estimator.

Abstract: Time delay and frequency offset calculation systems and related methods. System implementations include modules coupled together configured to calculate a time delay and a corresponding frequency offset of a second signal delayed in time relative to a first signal with the maximum value of a magnitude of a delay optimization function. Implementations of a method for calculating a time delay and frequency offset calculate the maximum value of the delay optimization function by generating the cross-correlation of one or more adjacent discrete Fourier transformed blocks corresponding to the first signal and second signal, respectively, of two or more discrete Fourier transformed blocks. The maximum value of the delay optimization function is then identified. Implementations of the method may compare the identified maximum value of the magnitude of the delay optimization function with a threshold to determine whether to continue processing for additional adjacent discrete Fourier transformed blocks.