Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.

Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Abstract: A maxilla holder includes a base plate and a connecting member. One end of the connecting member is connected with the base plate which extends along a pre-designed occlusal plane while the other end of the connecting member includes at least two supporting portions. With the supporting portions abutting against the cranium, the base plate is positioned so that the maxilla is located in a pre-planned position once it is moved onto the base plate.

Abstract: One aspect of the present disclosure pertains to a memory device. The memory device includes a semiconductor feature made of a compound semiconductor material. The semiconductor features includes a first portion as a first source/drain (S/D) feature, a second portion as a channel, and a third portion as a second S/D feature. The first portion is above the second portion and the second portion is above the third portion, and the second portion vertically extends from the first portion to the third portion. The memory device includes a gate structure horizontally wrapping around the second portion and a capacitor structure in direct contact with and wrapping around the semiconductor feature.

Abstract: A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.

Abstract: A thin-film deposition system deposits a thin-film on a wafer. A radiation source irradiates the wafer with excitation light. An emissions sensor detects an emission spectrum from the wafer responsive to the excitation light. A machine learning based analysis model analyzes the spectrum and detects contamination of the thin-film based on the spectrum.

Abstract: A pulmonary function identifying and treating method includes: obtaining a first image, having first image elements, and a second image, having second image elements, respectively corresponding to a first state and a second state of a lung; extracting first feature points of the first image and second feature points of the second image; registering the first image with the second image using a boundary point set registration method and an inner tissue registration method according to the first feature points and the second feature points, so that the first image elements correspond to the second image elements and tissue units of the lung; determining functional index values representative of the tissue units of the lung using a ventilation function quantification method according to the first image elements and the second image elements corresponding to the first image elements; and treating the lung according to the functional index values.

Abstract: A fibroblast activation protein (FAP) compound or salt is provided with albumin dual-binding function. It is a new target FAP molecule, comprising a payload group, a linker group and a FAP binding group. The linker group has an architecture selected from four architectures to connect to the payload group and the FAP binding group to form the FAP compound. The target FAP molecule has the biological activity of binding to albumin in blood and that of binding to FAP protein. The present invention is combined with radioactive nuclide Lu-177, Ac-225, Ga-67 or In-111 for long-circulation FAP targeting in the body. Higher accumulation in expressing FAP tumors is achieved, and the accumulation time of inhibitors in tumors is prolonged. The present invention allows radioactivity to act in the tumor for a long time, thereby reducing the radioactivity concentration or reducing the frequency of radioactive inhibitor administration to inhibit tumor growth.

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process. The process system then uses the selected process conditions data for the next etching process.

Abstract: A magnetic traction device for impacted tooth, comprising a first magnetic component fixed to a normal tooth and a second magnetic component fixed to an impacted tooth. There is an attractive magnetic force between the first and second magnetic components, thereby pulling the impacted tooth toward the direction of the normal tooth where the first magnetic component is located.

Abstract: A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.

Abstract: A gas dispenser utilized in a deposition apparatus is provided. The gas dispenser includes a showerhead comprising a plurality of holes, and a mask layer formed on a surface of the showerhead, wherein the holes penetrate through the mask layer. A deposition apparatus using the gas dispenser is also disclosed.

Abstract: A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

Abstract: A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

Abstract: The present application discloses a method for detecting cigarette appearance defects based on variational Bayesian inference. In a cigarette appearance defect detection scenario, in order to solve the problem that a current point estimation-based machine learning algorithm leads to an overconfidence decision in a data scarcity area, the present application proposes a variational inference-based Bayesian method to improve a SSD backbone network, preferably including calculating a real posterior probability by the variational inference method, replacing a point estimation mechanism of a convolution layer weight in the original backbone network by using a form of probability distribution, then detecting the improved extracted features by an SSD target detection algorithm, and furthermore, accurately determining whether the appearance of the cigarette is defective and the type and location of the defect.

Abstract: The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.

Abstract: Various embodiments of the present disclosure are directed to a vertical gate-all-around (GAA) memory cell. A middle conductor overlies a lower conductor and decreases in width towards the lower conductor to culminate in a point spaced from the lower conductor. An insulator structure is between the lower conductor and the middle conductor. A semiconductor channel overlies the middle conductor, and a gate electrode laterally surrounds the semiconductor channel on a sidewall of the semiconductor channel. A gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlies the semiconductor channel. The lower and middle conductors and the insulator structure correspond to a resistor, whereas the middle conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to a transistor atop the resistor.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.